Location-based noc interface with subtopologies

A computer program product embodied in a non-transitory computer readable medium for chip floor planning, the computer program product comprising code which causes one or more processors to perform operations of:

• accessing a system-on-chip (SoC), wherein the SoC includes one or more logic blocks;
• creating a network-on-a chip (NoC) topology, wherein the NoC topology includes one or more subtopologies, wherein the one or more subtopologies are based on a physical location of the one or more logic blocks, and wherein each subtopology in the one or more subtopologies includes at least one router;
• optimizing a location of the one or more subtopologies;
• and
• coupling the one or more subtopologies that were placed, wherein the coupling is based on one or more communications protocols.

A computer system for chip floor planning, comprising:

• a memory which stores instructions;
• one or more processors attached to the memory wherein the one or more processors, when executing the instructions which are stored, are configured to:
• access a system-on-chip (SoC), wherein the SoC includes one or more logic blocks;
• create a network-on-a chip (NoC) topology, wherein the NoC topology includes one or more subtopologies, wherein the one or more subtopologies are based on a physical location of the one or more logic blocks, and wherein each subtopology in the one or more subtopologies includes at least one router;
• optimize a location of the one or more subtopologies;
• and
• couple the one or more subtopologies that were placed, wherein the coupling is based on one or more communications protocols.