Waveform calculation using hybrid evaluation and simulation approach
AssigneeSynopsys, Inc.
InventorsAjay Singh Bisht, Alexander John Wakefield, Arjun Prasad Singh, Jayanta Roy, Nishikant Dubey
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Abstract
Aspects of the present disclosure relate to waveform calculation using a hybrid evaluation and simulation approach. Using one or more processors, one or more first portions of a design that are capable of being evaluated using waveform propagation are identified. The identified one or more first portions of the design are evaluated using waveform propagation. One or more second portions of the design that are not capable of being evaluated using waveform propagation are identified. Operation of the one or more second portions of the design is simulated.
Claims20
A method comprising:
- identifying, using one or more processors, one or more first portions of a design that are capable of being evaluated using waveform propagation;
- evaluating the identified one or more first portions of the design using waveform propagation;
- identifying one or more second portions of the design that are not capable of being evaluated using waveform propagation;
- simulating operation of the one or more second portions of the design;
- merging a waveform obtained by simulating operation of the one or more second portions with waveforms evaluated using waveform propagation to obtain a waveform set;
- evaluating the design for unknown signals based on the waveform set;
- and
- calculating power consumption of the design based on evaluating the design.
A method comprising:
- marking, using one or more processors, respective pins of circuit elements of a design that are capable of being evaluated using waveform propagation;
- evaluating the marked pins using waveform propagation, evaluating the marked pins including determining waveforms on respective ones of at least some of the marked pins;
- breaking loops in the design comprising marking, for each loop of the loops, a loop pin in the respective loop to store a waveform on the loop pin during simulation;
- identifying clusters of circuit elements of the design that are not capable of being evaluated using waveform propagation, wherein the clusters include the broken loops;
- and
- simulating operation of the clusters, the simulating using corresponding waveforms determined by the evaluation of the marked pins as input signals to the clusters, the simulating comprising storing waveforms of the marked loop pins determined in the simulation.
A non-transitory computer-readable storage medium comprising stored instructions, which when executed by one or more processors, cause the one or more processors to:
- mark respective pins of circuit elements of a design that are capable of being evaluated using waveform propagation comprising marking the respective pins as known waveforms, wherein, for a respective circuit element:
- where a pin of the respective circuit element that is mapped to a waveform, the pin is marked as a known waveform;
- where the respective circuit element has all input pins marked as known waveforms, an output pin of the respective circuit element is marked as a known waveform;
- and
- where a constant logical value is on an input pin of the respective circuit element and the constant logical value on the input pin and functionality of the respective circuit element result in a waveform on an output pin of the respective circuit element being known, the output pin of the respective circuit element is marked as a known waveform;
- and
- identify clusters of circuit elements of the design that are not capable of being evaluated using waveform propagation.
Dependencies are inferred from the claim text.