System level functional and performance verification across protocols/platforms using system analyzer

Abstract

System level functional and performance verification across protocols/platforms using a system analyzer that includes a protocol adaptor engine that includes multiple protocol adaptors that convert transactions of a circuit design from respective protocols of the circuit design to a unified protocol, to provide respective unified protocol transactions, and a core engine that includes multiple subsystem monitors configured to monitor respective user-defined subsystems of the circuit design, including to correlate upstream unified protocol transactions of the respective subsystems with downstream unified protocol transactions of the respective subsystems, perform integrity checks on the correlated unified protocol transactions, and report correlation and integrity checking results to an application manager. The application manager may permit user-configuration of the protocol adaptor engine, correlation policies, and/or integrity checking features.

Dependencies are inferred from the claim text.