Integrated circuit with accelerated boot to priority function

An integrated circuit (IC) comprising:

• multiple circuit elements including a phase locked loop (PLL);
• a processor;
• and
• a memory storing instructions that, when executed by the processor, cause the processor to:
• receive a component description that describes connections among the circuit elements;
• receive a list of specified peripherals to activate during a boot-up process of the IC;
• receive a hint data that describes a bypass mode clock frequency of the PLL;
• determine an operational data in response to the component description, the hint data, and the specified peripherals, wherein the operational data specifies a subset of the circuit elements, and wherein the subset of the circuit elements are required to make the specified peripherals operational;
• and
• initialize, and limit the initializing, to the subset of the circuit elements specified by the operational data.

An integrated circuit (IC) comprising:

• a processor;
• multiple public domain functional circuits;
• multiple secure domain functional circuits;
• and
• a first memory, a second memory, and an instruction memory;
• the instruction memory storing instructions that, when executed by the processor, cause the processor to:
• initiate a boot-up process of the IC;
• initialize the secure domain functional circuits;
• initialize the public domain functional circuits;
• load an authentication certificate corresponding to a software image into the first memory;
• load the software image into the second memory of the SoC;
• verify the authentication certificate in parallel with the loading the software image;
• wait for the loading of the software image action and the verify action to both complete successfully;
• authenticate the loaded software image using the verified authentication certificate;
• and
• execute the loaded software image in response to determining that the loaded software image is authentic.