Reconfigurable Processing Element for a Systolic Array

A systolic array for performing matrix multiplication of a first matrix and a second matrix to determine a result matrix, comprising:

• a plurality of reconfigurable processing elements that are configurable for operating in a weight stationary mode or in an output stationary mode, wherein each one of a first, second, third, fourth, and fifth reconfigurable processing element of the plurality of reconfigurable processing elements comprises:
• first and second input ports;
• first and second multiplexer circuitry;
• an internal register;
• a multiplier circuit;
• and
• an adder circuit, and wherein in the third reconfigurable processing element:
• the multiplier circuit generates a product of a number of the first matrix received from the first input port and a number of the second matrix received from the first multiplexer circuitry, wherein the first multiplexer circuitry routes the number of the second matrix from the internal register to the multiplier circuit in the weight stationary mode and from the second input to the multiplier circuit in the output stationary mode based on a control signal;
• and
• the adder circuit generates a sum of the product received from the multiplier circuit and a number of a partially determined element of the result matrix received from the second multiplexer circuitry, wherein the second multiplexer circuitry routes the number of the partially determined element of the result matrix from the second input port to the adder circuit in the weight stationary mode and from the internal register to the adder circuit in the output stationary mode based on the control signal.

A method of operating a reconfigurable processing element for a systolic array that is configured for performing matrix multiplication of a first matrix and a second matrix to determine a result matrix in a weight stationary mode or in an output stationary mode, wherein the reconfigurable processing element comprises first and second input ports, first and second multiplexer circuitry, an internal register, a multiplier circuit, and an adder circuit, comprising:

• with the first multiplexer circuitry, routing a number of the second matrix from the internal register to the multiplier circuit in the weight stationary mode and from the second input port to the multiplier circuit in the output stationary mode based on a control signal;
• with the multiplier circuit, generating a product of a number of the first matrix received from the first input port and the number of the second matrix received from the first multiplexer circuitry;
• with the second multiplexer circuitry, routing a number of a partially determined element of the result matrix from the second input port to the adder circuit in the weight stationary mode and from the internal register to the adder circuit in the output stationary mode based on the control signal;
• and
• with the adder circuit, generating a sum of the product received from the multiplier circuit and the number of the partially determined element of the result matrix received from the second multiplexer circuitry.