Distributed graphics processor unit architecture
AssigneeMicron Technology, Inc.
InventorDmitri Yudanov
Life of this patent
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Abstract
The present disclosure is directed to a distributed graphics processor unit (GPU) architecture that includes an array of processing nodes. Each processing node may include a GPU node that is coupled to its own fast memory unit and its own storage unit. The fast memory unit and storage unit may be integrated into a single unit or may be separately coupled to the GPU node. The processing node may have its fast memory unit coupled to both the GPU node and the storage node. The various architectures provide a GPU-based system that may be treated as a storage unit, such as solid state drive (SSD) that performs onboard processing to perform memory-oriented operations. In this respect, the system may be viewed as a “smart drive” for big-data near-storage processing.
Claims20
A device comprising:
- a set of registers;
- and
- a vector arithmetic logic unit (ALU), wherein the vector ALU is reconfigurable in response to a type of data or instructions received for processing to:
- operate as a single vector ALU,
- operate as multiple parallel vector ALUs,
- operate as multiple scalar ALUs, or
- operate as a combination of one or more parallel vector ALUs and one or more scalar ALUs.
A method comprising:
- receiving a set of instructions or data for processing;
- analyzing the received instructions or data to determine processing requirements;
- dynamically reconfiguring a vector arithmetic logic unit (ALU) based on the determined processing requirements, wherein the reconfiguration includes at least one of:
- configuring the vector ALU to operate as one of a single vector ALU, multiple parallel vector ALUs, multiple scalar ALUs, or a combination of one or more parallel vector ALUs and one or more scalar ALUs;
- and
- processing the received instructions or data using the reconfigured vector ALU.
A system comprising:
- a host processor;
- a memory;
- and
- a reconfigurable co-processor coupled to the host processor and the memory, the reconfigurable co-processor comprising:
- a vector arithmetic logic unit (ALU) capable of dynamically reconfiguring its architecture;
- a configuration controller coupled to the vector ALU and configured to:
- receive task information from the host processor,
- determine an optimal ALU configuration based on the task information, and
- instruct the vector ALU to reconfigure according to the determined optimal configuration, wherein the reconfiguration includes partitioning the vector ALU into one or more of:
- a single vector ALU, multiple parallel vector ALUs, multiple scalar ALUs, or a combination thereof.
Dependencies are inferred from the claim text.