Instruction set architecture for in-memory computing

A method, comprising:

• executing, by a general-purpose (GP) processor configured to communicate with a single co-processor, an instruction identifying a first address range of a first compute engine of a plurality of compute engines for data movement using the GP processor, each of the plurality of compute engines including a compute-in-memory (CIM) hardware module, the CIM hardware module configured to store a plurality of weights corresponding to a matrix in a plurality of storage cells and configured to perform a vector-matrix multiplication (VMM) of a vector and the matrix;
• at least one of writing first data to or loading the first data from the first address range corresponding to the first compute engine by the GP processor, the first data being for at least one of the plurality of weights, the vector, or a first output of the VMM of the vector and the matrix for the first compute engine;
• executing, by the GP processor, the instruction identifying a second address range for a second compute engine of the plurality of compute engines;
• at least one of writing second data to or loading the second data from the second address range corresponding to the second compute engine by the GP processor, the second data being for at least one of the plurality of weights, the vector, or a second output of the VMM of the vector and the matrix for the second compute engine;
• executing, by the GP processor, the instruction identifying a third address range for the first compute engine after the at least one of the writing the second data to or the loading the second data from the second address range;
• loading third data from the third address range by the GP processor, the third data being for the output of the VMM of the vector and the matrix for the first compute engine;
• and
• applying, by the GP processor to the third data from the third address range of the first compute engine, an activation function using a lookup table.

A compute tile, comprising:

• a plurality of compute engines, each of the plurality of compute engines including a compute-in-memory (CIM) hardware module, the CIM hardware module storing a plurality of weights corresponding to a matrix and configured to perform a vector-matrix multiplication (VMM) for the matrix;
• and
• a general-purpose (GP) processor coupled with the plurality of compute engines and configured to provide control instructions and data to the plurality of compute engines, wherein the GP processor is configured to:
• execute an instruction identifying a first compute engine of a plurality of compute engines to the GP processor;
• at least one of write first data to or load the first data from the first compute engine, the first data being for at least one of the plurality of weights, the vector, or a first output of the VMM of the vector and the matrix for the first compute engine;
• execute the instruction identifying a second compute engine of the plurality of compute engines to the GP processor after the at least one of writing first data to or loading the first data from the first compute engine;
• and
• at least one of write second data to or load the second data from the second compute engine, the second data being for at least one of the plurality of weights, the vector, or a second output of the VMM of the vector and the matrix for the second compute engine;
• wherein the GP processor provides control and data movement for the plurality of compute engines.