Memory module with timing-controlled data buffering

A memory module operable in a computer system to communicate with a memory controller of the computer system via a memory bus including control and address (C/A) signal lines and a data bus, the memory module comprising:

• a module board having edge connections corresponding to respective signal lines in the memory bus;
• a module control device mounted on the module board, and configurable to receive via the C/A signal lines first input C/A signals corresponding to a first operation and subsequently a second input C/A signals corresponding to a second operation, and to output first module control signals in response to the first input C/A signals and second module control signals in response to the second input C/A signals;
• memory devices mounted on the module board and arranged in multiple ranks on the module board;
• and
• data buffers coupled between the edge connections and the memory devices, and configurable to receive the first module control signals and subsequently the second module control signals from the module control device, wherein a respective data buffer of the data buffers is coupled to at least one respective memory device in each of the multiple ranks and includes a respective delay control circuit configurable to receive data signals corresponding to the second operation from at least one respective memory device in a selected rank of the multiple ranks and to adjust timing of at least one of the data signals based at least on one or more of the first module control signals, the selected rank being selected to perform the second operation in response to the second input C/A signals, the second operation being a read operation.