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US 2025/0028659 A1Published application
Multiple pin configurations of memory devices
AssigneeMicron Technology, Inc.
InventorJunichi Sato
Life of this patent
Estimating the term…
Abstract
An apparatus configured to allow data values to be written into the plurality of memory cells of the memory device at a first speed upon connecting to a first host via a first configuration of the plurality of connectors; and allow data values to be written into the plurality of memory cells at a second speed faster than the first speed, upon connecting to a second host via a second configuration of the plurality of connectors.
Claims20
A device, comprising:
- memory cells;
- a communication interface;
- an integrated circuit package configured to enclose the memory cells and the communication interface;
- and
- a plurality of connectors coupled to the communication interface to provide connections from the communication interface to outside of the integrated circuit package;
- wherein the communication interface is adaptable to use the plurality of connectors in a first configuration to access the memory cells from the outside of the integrated circuit package at a first speed and to use the plurality of connectors in a second configuration to access the memory cells from the outside of the integrated circuit package at a second speed different from the first speed.
3 more elements
A method, comprising:
- determining, by a communication interface of a device having memory cells and the communication interface enclosed within an integrated circuit package, a current configuration of a plurality of connectors of the device being connected to outside of the integrated circuit package;
- and
- communicating data, through the communication interface with the outside of the integrated circuit package, at a first speed when the current configuration is a first configuration, or at a second speed, different from the first speed, when the current configuration is a second configuration.
An apparatus, comprising:
- a processing device;
- and
- a memory device having:
- memory cells;
- a communication interface;
- an integrated circuit package configured to enclose the memory cells and the communication interface;
- and
- a plurality of connectors coupled to the communication interface to provide connections from the communication interface to the processing device;
- wherein the communication interface is adaptable to use the plurality of connectors in a first configuration for the processing device to access the memory cells at a first speed and to use the plurality of connectors in a second configuration for the processing device to access the memory cells at a second speed different from the first speed.
6 more elements
Dependencies are inferred from the claim text.