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US 2025/0028652 A1Published application
Victim cache with dynamic allocation of entries
OwnerNaveen BHORIA, Timothy David ANDERSON +1inventors
InventorsNaveen BHORIA, Timothy David ANDERSON, Pete HIPPLEHEUSER
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Abstract
A caching system including a first sub-cache, and a second sub-cache coupled in parallel with the first sub-cache; wherein the second sub-cache includes line type bits configured to store an indication that a corresponding line of the second sub-cache is configured to store write-miss data.
Claims20
A system comprising:
- a first sub-cache;
- a second sub-cache;
- and
- a cache controller,
- wherein:
- the second sub-cache includes a set of lines and a set of line type bits, wherein each line type bit of the set of line type bits corresponds to a respective line of the set of lines;
- each line of the set of lines is configured to operate in a first manner to store data associated with a write-miss or a second manner to store data associated with an eviction of a cache entry from the first sub-cache;
- and
- the cache controller is configured to determine, based on whether a line of the set of lines operates in the first manner or the second manner, whether to store a first indication in a line type bit of the set of line type bits corresponding to the line to indicate that data stored in the line is associated with a write-miss or a second indication to indicate that the data is associated with an eviction of a cache entry from the first sub-cache.
6 more elements
A method, comprising:
- receiving a write memory request specifying to write first data to a caching system, wherein the caching system includes a first sub-cache and a second sub-cache, and wherein the second sub-cache includes a set of lines and a set of line type bits, each line type bit of the set of line type bits corresponding to a respective line of the set of lines;
- determining whether the write memory request corresponds to a write miss in the first sub-cache;
- determining whether the write memory request corresponds to a write miss in the second sub-cache;
- and
- determining, based on whether the write memory request corresponds to a write miss in the first sub-cache and the second sub-cache, whether to store a first indication in a first line type bit of the set of line type bits corresponding to a first line of the set of lines to indicate that data stored in the first line is associated with a write-miss.
2 more elements
A device, comprising:
- a processor configured to provide a write memory request for a memory address;
- and
- a caching system comprising:
- a first sub-cache;
- and
- a second sub-cache including a set of lines and a set of line type bits, each line type bit of the set of line type bits corresponding to a respective line of the set of lines,
- wherein the caching system is configured to:
- determine whether the memory address is cached in the first sub-cache of the caching system;
- determine whether the memory address is cached in the second sub-cache of the caching system;
- and
- determine, based on whether the memory address is cached in the first sub-cache and the second sub-cache, whether to store a first indication in a first line type bit of the set of line type bits corresponding to a first line of the set of lines to indicate that data stored in the first line is associated with a write-miss.
8 more elements
Dependencies are inferred from the claim text.