Memory pooling bandwidth multiplier using final level cache system

A method of operating a data access system, wherein the data access system comprises a processor having processor cache, a switch fabric, a switch connected memory, a first final level cache (FLC) module which includes a first FLC controller and a first DRAM and a second FLC module which includes a second FLC controller and a second DRAM, the method comprising:

• generating, with the processor, a request for data which includes a physical address;
• providing the request for data to the first FLC module;
• determining if the first FLC controller contains the physical address;
• responsive to the first FLC controller containing the physical address, retrieving the data from the first DRAM and providing the data to the processor;
• responsive to the first FLC controller not containing the physical address, forwarding the request for data and the physical address directly to the second FLC module, wherein the first FLC controller and the second FLC controller are on a same die;
• determining if the second FLC controller contains the physical address;
• responsive to the second FLC controller not containing the physical address, forwarding the request for data and the physical address to the switch fabric;
• routing, with the switch fabric, the request for data and the physical address to the switch connected memory;
• and
• retrieving the data identified by the request for data from the switch connected memory and providing the data through the switch fabric to the second FLC module, the first FLC module, and the processor, wherein the switch connected memory is a shared resource.

A memory storage and access system comprising:

• two or more processors, each having a processor cache, the two or more processors configured to generate data requests for data;
• two or more final level cache (FLC) cache systems, each configured to receive the data requests, wherein each FLC cache system comprises:
• a first FLC module having a first FLC controller and first memory, the first FLC module processing the data requests from the processor;
• a second FLC module, directly connected to and on a same die as the first FLC module, having a second FLC controller and second memory, the second FLC module, responsive to the first FLC module not having the data requested by the processor, receiving and processing the data requests from the first FLC module;
• and
• two or more switch fabrics, of which two or more are connected to switch fabric accessible memory, such that each of the two or more switch fabric connect to at least one of the two or more FLC cache systems wherein the switch fabric accessible memory is configured to receive the data requests from the second FLC module responsive to the second FLC module not having the data, and the switch fabric accessible memory is shared by the two or more FLC cache systems as a shared memory pool.