Look-up table-based in-memory computing system
AssigneeUniversity of Florida Research Foundation, Inc.
InventorsBaibhab Chatterjee, Swarup Bhunia, Peyman Dehghanzadeh
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Abstract
A method and system are directed to providing a look-up table (LUT)-based computation method targeted toward compute-in-memory (CiM) applications. The method comprises a divide and conquer-based approach to provide a solution to scalability challenges in LUT-based mathematical operations for CiM applications. The divide and conquer approach distributes a complex operation into smaller, less complex operations.
Claims20
A method for performing computations, the method comprising:
- generating one or more most significant bit sub-operations and a least significant bit sub-operation that are associated with a computing operation;
- retrieving, based on a first input operand and a second input operand, one or more select results from a plurality of results that are associated with the one or more most significant bit sub-operations and the least significant bit sub-operation from a memory array, wherein the one or more select results comprises one or more most significant bit sub-operation results and a least significant bit sub-operation result;
- generating one or more left-shifted most significant bit sub-operation results that are associated with the one or more most significant bit sub-operation results based on a determination that the computing operation comprises a multiplication operation;
- and
- generating a result of the computing operation based on an addition operation of the one or more left-shifted most significant bit sub-operation results and the least significant bit sub-operation result.
A system for performing computations, the system comprising:
- a most significant bit multiplexer that is configured to generate a most significant bit sub-operation result that is associated with a computing operation based on a first input operand and a second input operand;
- a least significant bit multiplexer that is configured to generate a least significant bit sub-operation result that is associated with the computing operation;
- one or more shift registers that are configured to generate a left-shifted most significant bit sub-operation result;
- and
- a plurality of adders that are configured to generate a computing operation output by adding the left-shifted most significant bit sub-operation result with the least significant bit sub-operation result.
A computing system comprising memory and one or more processors communicatively coupled to the memory, the one or more processors configured to:
- generate one or more most significant bit sub-operations and a least significant bit sub-operation that are associated with a computing operation;
- retrieve, based on a first input operand and a second input operand, one or more select results from a plurality of results that are associated with the one or more most significant bit sub-operations and the least significant bit sub-operation from a memory array, wherein the one or more select results comprises one or more most significant bit sub-operation results and a least significant bit sub-operation result;
- generate one or more left-shifted most significant bit sub-operation results that are associated with the one or more most significant bit sub-operation results based on a determination that the computing operation comprises a multiplication operation;
- and
- generate a result of the computing operation based on an addition operation of the one or more left-shifted most significant bit sub-operation results and the least significant bit sub-operation result.
Dependencies are inferred from the claim text.