Electrostatic Discharge Detection and Data Storage Device Reaction

Abstract

Instead of allowing an electrostatic discharge (ESD) event to cause a lost clock signal sync due effects of the ESD event causing an SSD to enter low power mode, utilizing ESD detection can be used to stop the reference clock signal to avoid involuntary low power mode. When an ESD event occurs, an ESD antenna sensor will selectivity disable sensitive signals and the reference clock signal. Once the ESD detector recognizes an ESD event has occurred, the device is able to enter freeze mode. While the reference clock signal is in freeze mode, the input signals are bypassed to avoid lost clock signal sync. Once the ESD event is done, the controller notifies the host to restart the reference clock signal and resume clock signal sync.

Dependencies are inferred from the claim text.