US 2025/0028565 A1 · SCHEDULE-AWARE DYNAMICALLY RECONFIGURABLE ADDER TREE ARCHITECTURE FOR PARTIAL SUM ACCUMULATION IN MACHINE LEARNING ACCELERATORS

Abstract

Embodiments of the present disclosure are directed toward techniques and configurations enhancing the performance of hardware (HW) accelerators. The present disclosure provides a schedule-aware, dynamically reconfigurable, tree-based partial sum accumulator architecture for HW accelerators, wherein the depth of an adder tree in the HW accelerator is dynamically based on a dataflow schedule generated by a compiler. The adder tree depth is adjusted on a per-layer basis at runtime. Configuration registers, programmed via software, dynamically alter the adder tree depth for partial sum accumulation based on the dataflow schedule. By facilitating a variable depth adder tree during runtime, the compiler can choose a compute optimal dataflow schedule that minimizes the number of compute cycles needed to accumulate partial sums across multiple processing elements (PEs) within a PE array of a HW accelerator. Other embodiments may be described and/or claimed.

Claims20

Dependent claims

An apparatus with a plurality of levels, the plurality of levels comprising:

a first level comprising accumulation elements and storage elements, each accumulation element in the first level coupled with a respective storage element in the first level and two or more processing elements in a processing element group;
and
a second level comprising one or more accumulation elements and one or more second storage elements, each accumulation element in the second level coupled with a respective storage element in the second level and two or more accumulation elements in the first level,
wherein a level is selected from the plurality of levels based on a factor indicating a distribution of input channels of a neural network operation to one or more processing elements in the processing element group, and a storage element in the selected level stores an output of the apparatus.

1 more element

Dependencies are inferred from the claim text.

Schedule-aware dynamically reconfigurable adder tree architecture for partial sum accumulation in machine learning accelerators

Life of this patent

Schedule-aware dynamically reconfigurable adder tree architecture for partial sum accumulation in machine learning accelerators

Life of this patent

Abstract

Claims20