Vector dataflow architecture for embedded systems
AssigneeCarnegie Mellon University
InventorsBrandon Lucia, Nathan Beckmann, Graham Gobieski
Life of this patent
Estimating the term…
Abstract
Disclosed herein is a highly energy-efficient architecture targeting the ultra-low-power sensor domain. The architecture achieves high energy-efficiency while maintaining programmability and generality. The invention introduces vector-dataflow execution, allowing the exploitation of the dataflows in a sequence of vector instructions and to amortize instruction fetch and decode over a whole vector of operations. The vector-dataflow architecture allows the invention to avoid costly vector register file accesses, thereby saving energy.
Claims21
A processor architecture implementing a vector-dataflow execution model comprising:
- a scalar processor core;
- a vector processor core with a single execution unit;
- issue logic;
- a register renaming table;
- an instruction window buffer;
- an xdata buffer;
- and
- a forwarding buffer;
- wherein the xdata buffer stores additional information from a scalar register file needed by instructions executed by the vector processor core.
A processor architecture implementing a vector-dataflow execution model comprising:
- a vector processor with a single-lane;
- an in-order scalar processor core;
- instruction windowing hardware;
- and
- a renaming mechanism.
Dependencies are inferred from the claim text.