Mechanism for efficient massively-concurrent conditional computation

A chip, comprising:

• at least one processing core;
• a controller circuit operatively coupled to the at least one processing core;
• and
• an instruction memory in communication with the controller circuit, the instruction memory having stored therein a program comprising a plurality of instructions, wherein the controller circuit is configured to:
• select a plurality of conditional instructions from the plurality of instructions, the plurality of conditional instructions having a plurality of relational operators;
• concurrently compute the plurality of relational operators on a plurality of inputs, resulting in a plurality of results;
• combine the plurality of results to determine an index;
• select an operation based on the index;
• and
• cause the at least one processing core to execute the selected operation.