Zero-clearing scalar moves

A non-transitory machine readable medium storing at least an instance of a single instruction which when processed by a processor is to cause a method to be performed, the method comprising:

• decoding the instance of the single instruction, the instance of the single instruction to include one or more fields for an opcode, one or more fields to indicate a source operand location, and one or more fields to indicate a destination operand location, wherein the opcode is to indicate a copy of data element of an indicated size of 16-bit or 32-bit from the indicated source operand location to the indicated destination operand location, wherein when:
• 1) the indicated source operand location is a packed data register and the indicated destination operand location is a packed data register, the data element to be copied is a data element in a least significant data element position of the indicated source operand location and the data element is to be copied into in a least significant data element position of the indicated destination operand location with all other data element positions of the indicated destination operand are to be zeroed,
• 2) the indicated source operand location is a packed data register and the indicated destination operand location is a memory location, the data element to be copied is a data element in a least significant data element position of the indicated source operand location and the data element is to be copied into the memory location, and
• 3) the indicated source operand location is a memory location and the indicated destination operand location is a packed data register, the data element of the memory location is to be copied into in a least significant data element position of the indicated destination operand location with all other data element positions of the indicated destination operand are to be zeroed;
• and
• executing the decoded instance of the single instruction according to the opcode.

A system comprising:

• memory to store an instance of a single instruction;
• decoder circuitry to decode the instance of the single instruction, the instance of the single instruction to include one or more fields for an opcode, one or more fields to indicate a source operand location, and one or more fields to indicate a destination operand location, wherein the opcode is to indicate a copy of data element of an indicated size of 16-bit or 32-bit from the indicated source operand location to the indicated destination operand location, wherein when:
• 1) the indicated source operand location is a packed data register and the indicated destination operand location is a packed data register, the data element to be copied is a data element in a least significant data element position of the indicated source operand location and the data element is to be copied into in a least significant data element position of the indicated destination operand location with all other data element positions of the indicated destination operand are to be zeroed,
• 2) the indicated source operand location is a packed data register and the indicated destination operand location is a memory location, the data element to be copied is a data element in a least significant data element position of the indicated source operand location and the data element is to be copied into the memory location, and
• 3) the indicated source operand location is a memory location and the indicated destination operand location is a packed data register, the data element of the memory location is to be copied into in a least significant data element position of the indicated destination operand location with all other data element positions of the indicated destination operand are to be zeroed;
• and
• execution circuitry to execute the decoded instance of the single instruction according to the opcode.