Multiplication circuitry, system, chip-containing product, and computer-readable medium

Multiplication circuitry comprising:

• a plurality of adder sub-arrays, each adder array to add a respective set of partial products to generate one or more sub-array result values representing a result of signed multiplication of a respective pair of portions of bits selected from a first operand and a second operand, the plurality of adder sub-arrays comprising separate instances of hardware circuitry, the plurality of adder sub-arrays having at least two separate enable control signals for independently controlling whether at least two subsets of the adder sub-arrays are enabled or disabled;
• and
• a result assembly adder array to perform a result assembly addition to add a plurality of assembled values including the sub-array result values generated by the plurality of adder sub-arrays, to generate at least one multiplication result value representing a result of signed multiplication of the first operand and the second operand;
• wherein for a sign-extension-emulated sub-array result value being added in the result assembly addition, the result assembly adder array is configured to perform sign extension emulation by:
• applying a default zero extension to the sign-extension-emulated sub-array result value regardless of a sign of the sign-extension-emulated sub-array result value, and
• performing the result assembly addition with at least one other of the plurality of assembled values having a value that, when added in the result assembly addition, emulates an effect of sign extending the sign-extension-emulated sub-array result value up to a bit position corresponding to the most significant bit of the at least one multiplication result value.