Systems and methods for providing asynchronous read/write support in ddr controllers

A system for supporting asynchronous READ/WRITE operations in a Double Data Rate (DDR) controller, comprising:

• a READ module of a computing device configured to invoke an async memget function and transmit an async-READ data command for the invoked async memget function to the DDR controller for performing an asynchronous READ operation;
• a WRITE module of the computing device configured to invoke an async memset function and transmit an async-WRITE data command for the invoked async memset function to the DDR controller, the async memset function being for performing an asynchronous WRITE operation, wherein the computing device proceeds with other operations in an unblocked independent manner after transmitting one of the async-READ data command and the async-WRITE data command to the DDR controller, the one of the async-READ data command and the async-WRITE data command being for implementing one of the async memget function and the async memset function respectively;
• and
• a DDR trigger module of the DDR controller configured to trigger one of a read operation and a write operation after receiving one of the async-READ data command and the async-WRITE data command from the READ module and the WRITE module of the computing device, the read operation and the write operation being for generating a memory access request to access a Dynamic Random Access Memory (DRAM).

A computing device, comprising:

• a processor, configured to:
• invoke one of an async memget function for performing an asynchronous READ operation and an async memset function for performing an asynchronous WRITE operation;
• and
• transmit one of an async-READ data command and an async-WRITE data command for the invoked async memget function and the async memset function to a Double Data Rate (DDR) controller, wherein the processor proceeds with other operations in an unblocked independent manner after transmitting one of the async-READ data command and the async-WRITE data command to the DDR controller for implementing one of the async memget function and the async memset function respectively, wherein the DDR controller triggers one of a read operation and a write operation after receiving one of the async-READ data command and the async-WRITE data command from the processor, the one of the read operation and the write operation being for generating a memory access request to access a Dynamic Random Access Memory (DRAM).