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US 2025/0028467 A1Published application
Block copy
AssigneeRambus Inc.
InventorsMichael Raymond MILLER, Steven C. Woo, Thomas Vogelsang
Life of this patent
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Abstract
An interconnected stack of one or more Dynamic Random Access Memory (DRAM) die also has one or more custom logic, controller, or processor die. The custom die(s) of the stack include direct channel interfaces that allow direct access to memory regions on one or more DRAMs in the stack. The direct channels are time-division multiplexed such that each DRAM die is associated with a time slot on a direct channel. The custom die configures a first DRAM die to read a block of data and transmit it via the direct channel using a time slot that is assigned to a second DRAM die. The custom die also configures the second memory device to receive the first block of data in its assigned time slot and write the block of data.
Claims21
(canceled)
An integrated circuit stack, comprising:
- a set of stacked memory integrated circuits comprising a first memory device, a second memory device, and a third memory device, each comprising memory cell arrays;
- a controller electrically coupled to, and stacked with, the set of stacked memory devices comprising at least a portion of the integrated circuit stack;
- and
- intra-device interconnect coupling the controller, the first memory device, the second memory device, and the third memory device to each other, the controller to configure the first memory device to read a first block of data from at least a first memory cell array of the first memory device and to transmit, in a first transmission, the first block of data via the intra-device stack interconnect, the controller to also configure the second memory device and the third memory device to receive the first block of data via the first transmission, the controller to also configure the second memory device to write the first block of data transmitted by the first memory device in the first transmission to at least a second memory cell array of the second memory device and the controller to also configure the third memory device to write the first block of data transmitted by the first memory device in the first transmission to at least a third memory cell array of the third memory device.
1 more element
An integrated circuit stack, comprising:
- a set of stacked integrated circuit memory devices that include a first memory device, a second memory device, and a third memory device, the set of stacked memory devices each comprising memory cell circuitry;
- and
- a processing device electrically coupled to, and stacked with, the set of stacked memory devices to form a first device stack, the processing device comprising a controller, the controller to communicate data with the first set of stacked memory devices using time-division multiplexing wherein respective ones of the set of stacked memory devices communicate data with the controller using respective ones of a set of non-overlapping and periodically repeating time slots that repeat at a frequency, the first memory device to communicate data with the controller using a first non-overlapping and periodically repeating time slot of the set of non-overlapping and periodically repeating time slots, the second memory device to communicate data with the controller using a second non-overlapping and periodically repeating time slot of the set of non-overlapping and periodically repeating time slots, the third memory device communicate data with the controller using a third non-overlapping and periodically repeating time slot of the set of non-overlapping and periodically repeating time slots, the controller to configure the first memory device to transmit a block of data directly to the second memory device using at least one instance of the second non-overlapping and periodically repeating time slot without the data being re-transmitted by the controller, the controller to configure the first memory device to transmit the block of data directly to the third memory device using at least one instance of the third non-overlapping and periodically repeating time slot without the data being re-transmitted by the controller, the controller to configure the second memory device to write the block of data transmitted by the first memory device in the at least one instance of the second non-overlapping and periodically repeating time slot to memory cell circuitry of the second memory device, the controller to configure the third memory device to write the block of data transmitted by the first memory device in the at least one instance of the third non-overlapping and periodically repeating time slot to memory cell circuitry of the third memory device.
A controller, comprising:
- a command/address interface to communicate commands and addresses with a plurality of stacked memory devices via first set of shared interconnections using respectively assigned time-division multiplexing slots to address commands and addresses transmitted by the controller to all of the plurality of stacked memory devices, to respective ones of the plurality of stacked memory devices, each of the first set of shared interconnections being connected with each of the plurality of stacked memory devices;
- and
- a data interface to communicate data with a plurality of the plurality of stacked memory devices via a second set of shared interconnections using time-division multiplexing that uses a plurality of ones of a set of non-overlapping and periodically repeating time slots assigned to respective ones of the plurality of stacked memory devices to address data communication between the controller and respectively addressed plurality of ones of the plurality of stacked memory devices, each of the second set of shared interconnections being connected with each of the plurality of stacked memory devices.
Dependencies are inferred from the claim text.