Many-Core Definable Distributed Shared Storage Structure

A many-core definable distributed shared storage structure, comprising:

• an internal data bus system, comprising a transverse bidirectional data line, a longitudinal bidirectional data line, and a processor core storage access bus;
• a plurality of routing units, each arranged at an intersection of the transverse bidirectional data line and the longitudinal bidirectional data line, and configured to transmit data;
• a plurality of processor cores, each connected to the routing unit via a network interface unit;
• a plurality of the network interface units, each connected to the routing unit through the processor core storage access bus;
• and
• a plurality of memory module, each connected to the routing unit directly,
• wherein the plurality of the memory modules constitute a storage structure system inside a many-core processor,
• wherein each network interface unit includes:
• a configuration package parsing unit, configured to parse a configuration package input from the routing unit, by judging an operation type by a packet header, extracting address information and data information in the configuration package, and combining the operation type, the address information and the data information to obtain a routing configuration instruction and a routing control instruction for outputting the same to a routing table, wherein the routing configuration instruction comprises the address information, the data information and a first writing signal;
• the routing control instruction comprises memory module grouping flag information, memory module ping pong reading and writing control information, and a second writing signal;
• a data packet assembling/parsing unit, responsible for data format conversion between the processor core and the routing unit, and obtaining a valid data by parsing a data packet received from the corresponding routing unit;
• and configured to convert a reading and writing data output from the processor core and a physical coordinate position of a destination memory module output from the routing table to an network-on-chip transmittable data packet, and output the same to the corresponding routing unit, wherein the packet header of the data packet comprises the physical coordinate position of the destination memory module output from the routing table;
• and
• the routing table, configured to receive an address signal output from the processor core, judge and query a physical coordinate position of a destination memory module corresponding to said address signal, and output said physical coordinate position to the data packet assembling/parsing unit;
• configured to write-in and change all fields in line with the routing configuration instruction;
• and configured to write-in and change a routing control field in the routing table in line with the routing control instruction.