Field programmable gate array device including spin orbit torque-magnetic random access memory and operating method thereof

An operating method of a field programmable gate array device which includes a cell array including a plurality of cells, a drive circuit connected to the cell array through a plurality of word lines, and a peripheral circuit connected to the cell array through a plurality of bit lines and a plurality of source lines and configured to control the drive circuit, the method comprising:

• receiving, at the drive circuit, first input signals from an external device;
• driving, at the drive circuit, a first word line, among the plurality of word lines, based on the first input signals;
• receiving, at the peripheral circuit, a command, an address, and a second input signal from the external device;
• and
• performing, at the peripheral circuit, a data read operation on a first cell, among cells connected to the first word line from among the plurality of cells, based on the command and the second input signal,
• wherein each of the cells connected to the first word line is connected to two of the plurality of bit lines and one of the plurality of source lines.

An operating method of a field programmable gate array device which includes a cell array including a plurality of cells, a drive circuit connected to the cell array through a plurality of word lines, and a peripheral circuit connected to the cell array through a plurality of bit lines and a plurality of source lines and configured to control the drive circuit, the method comprising:

• receiving, at the drive circuit, first input signals from an external device;
• driving, at the drive circuit, a first word line among the plurality of word lines based on the first input signals;
• receiving, at the peripheral circuit, a write command, a write address, write data, and a second input signal from the external device;
• writing, at the peripheral circuit, the write data to a first cell among cells connected to the first word line from among the plurality of cells, based on the write command and the second input signal;
• receiving, at the peripheral circuit, a read command, a read address, and the second input signal from the external device;
• and
• reading, at the peripheral circuit, a second cell, among the cells connected to the first word line from among the plurality of cells, based on the read command and the second input signal,
• wherein the writing of the write data includes
• performing, at the peripheral circuit, first logical operations with respect to the second input signal and a write enable signal,
• applying, at the peripheral circuit, different voltages to the plurality of source lines based on the first input signals and the second input signal, and
• writing, at the peripheral circuit, the write data to the first cell of the plurality of cells based on the voltages and a result of the first logical operations,
• wherein the write enable signal is generated by the peripheral circuit in response to the write command,
• wherein the reading of the second cell among the cells connected to the first word line from among the plurality of cells includes
• performing, at the peripheral circuit, second logical operations with respect to the second input signal and the read command, and
• sensing, at the peripheral circuit, a voltage change of a bit line, which is connected to the second cell among the plurality of cells, from among the plurality of bit lines based on a result of the second logical operations,
• wherein the read enable signal is generated by the peripheral circuit in response to the read command, and
• wherein each of the cells connected to the first word line is connected to two of the plurality of bit lines and one of the plurality of source lines.