Semiconductor memory device and memory system including the same

A semiconductor memory device comprising:

• a memory cell array including a plurality of memory cell rows, wherein each of the plurality of memory cell rows comprises a respective plurality of memory cells;
• and
• a row hammer management circuit comprising a hammer address queue, the row hammer management circuit configured to perform operations comprising:
• receiving an active command associated with a first memory cell row of the plurality of memory cell rows;
• comparing a first count data associated with the first memory cell row with a first reference number, wherein the first count data represents a number of times the first memory cell row have been accessed and is stored in a first count cell associated with the first memory cell row;
• storing a first row address of the first memory cell row as one of candidate hammer addresses in the hammer address queue based on the first count data being equal to or greater than the first reference number;
• generating a random first count data by randomly updating the first count data based on an activation of an event signal, the event signal representing a state of the hammer address queue;
• and
• storing the random first count data in the first count cell.