US 2025/0027996 A1 · MONITOR CIRCUIT TO DETERMINE INTEGRATED CIRCUIT CONDITION BASED ON DIAGNOSTIC CODE SEQUENCE

Abstract

Aspects relate to monitoring timing margin of logic paths and its degradation through an integrated circuit. In one example an apparatus includes an integrated circuit having a logic path formed in the integrated circuit and a monitor circuit formed in the integrated circuit. The monitor circuit is configured to monitor a condition of the logic path and to generate a diagnostic code sequence to indicate the condition of the logic path over time. A monitor controller is configured to receive diagnostic codes of the diagnostic code sequence, to store the diagnostic codes in a log with a corresponding time stamp and to determine a condition of the integrated circuit based on the diagnostic code sequence.

Claims20

Dependent claims

An apparatus comprising:

an integrated circuit having a logic path formed in the integrated circuit;
a monitor circuit formed in the integrated circuit, the monitor circuit being configured to monitor a condition of the logic path and to generate a diagnostic code sequence to indicate the condition of the logic path over time;
and
a monitor controller configured to receive diagnostic codes of the diagnostic code sequence, to store the diagnostic codes in a log with a corresponding time stamp and to determine a condition of the integrated circuit based on the diagnostic codes.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

18/482,703Filed 6 Oct 2023

Priority

20 Jul 2023

Published

23 Jan 2025

Term ends

Not estimatedThe source records don’t support an estimate.

Classification13 codes

G06F 30/343
For reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]: logical level
G01R 31/2882
Testing of integrated circuits [IC]: testing timing characteristics
G01R 31/3016
Marginal testing, e.g. by varying supply voltage: delay or race condition test, e.g. race hazard test
G01R 31/31725
Testing of digital circuits: timing aspects, e.g. clock distribution, skew, propagation delay

Monitor circuit to determine integrated circuit condition based on diagnostic code sequence

Life of this patent

Monitor circuit to determine integrated circuit condition based on diagnostic code sequence

Life of this patent

Abstract

Claims20