Clock gating circuits and methods for dual-edge-triggered applications

A system, comprising:

• a first digital logic circuit;
• a first latch circuit coupled to the first digital logic circuit;
• a second digital logic circuit coupled to the first latch circuit;
• and
• a second latch circuit coupled to the second digital logic circuit,
• wherein the first digital logic circuit is configured to receive an input clock signal and provide an output signal based on a state of the input clock signal;
• wherein the first latch circuit is configured to receive an enable signal at a control pin of the first latch circuit, receive the output signal at a data pin of the first latch circuit, and provide, based on states of the enable signal and the input clock signal, a select signal;
• wherein the second digital logic circuit is configured to receive the input clock signal, receive the select signal, and provide, based on states of the input clock signal and the select signal, one of the input clock signal or an inverted input clock signal;
• and
• wherein the second latch circuit is configured to receive the enable signal at a control pin of the second latch circuit, receive the one of the input clock signal or the inverted input clock signal at a data pin of the second latch circuit, and output, based on states of the enable signal and the one of the input clock signal or the inverted input clock signal, a gated clock signal.

A method, comprising:

• generating, by a first digital logic circuit, a first output signal based on an input clock signal and an output clock signal, wherein the output clock signal represents a gated version of the input clock signal;
• generating, by a first latch circuit, a select signal based on an enable signal and the first output signal;
• generating, by a second digital logic circuit, a second output signal based on the input clock signal and the select signal;
• generating, by a second latch circuit, the output clock signal based on the enable signal and the second output signal;
• and
• providing the output clock signal to a dual-edge triggered flip-flop.