Test-time optimization with few slow scan pads
AssigneeSTMicroelectronics International N.V.
InventorsSandeep JAIN, Shalini PATHAK, Pooja JAIN
Life of this patent
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Abstract
An integrated circuit improves scan testing efficiency by addressing slow Scan-OUT pins. The integrated circuit shifts data through high-frequency Scan-OUT pins every cycle and through low-frequency Scan-OUT pins every other cycle. Data that cannot be shifted through low-frequency pins is stored in an accumulator and later shifted out through high-frequency pins. Despite changing the scan-out data pattern, the tester used for testing the integrated circuit anticipates the resulting pattern, providing for the testing to not be negatively impacted.
Claims16
An integrated circuit, comprising:
- a scan compressor configured to compress output scan data as the output scan data is shifted out from scan chains;
- a plurality of scan-out pads, wherein a first group of the plurality of scan-out pads operates at a first scan frequency, and a second group of the plurality of scan-out pads operates at a second scan frequency that is lower than the first scan frequency;
- first scan-out circuitry configured to shift a first portion of the output scan data out through the first group of the plurality of scan-out pads at the first scan frequency;
- second scan-out circuitry configured to shift every other bit of a second portion of the output scan data out through the second group of the plurality of scan-out pads at the second scan frequency;
- and
- an accumulator configured to accumulate bits of the second portion of the output scan data that were not shifted out through the second group of the plurality of scan-out pads;
- wherein the first scan-out circuitry is further configured to, after shifting out the first portion of the output scan data at the first scan frequency, shift at least a portion of the accumulated bits out through the first group of the plurality of scan-out pads at the first scan frequency.
A method of performing scan-testing on an integrated circuit, comprising:
- during a first operating period:
- shifting scan patterns through scan chains and out through a scan compressor as output scan data;
- shifting a first portion of the output scan data out through a first group of scan-out pads at a first scan frequency;
- shifting every other bit of a second portion of the output scan data out through a second group of scan-out pads at a second scan frequency less than the first scan frequency;
- and
- accumulating bits of the second portion of the output scan data that were not shifted out through the second group of scan-out pads;
- and
- during a second operating period immediately after the first operating period:
- shifting at least a portion of the accumulated bits out through the first group of scan-out pads at the first scan frequency.
Dependencies are inferred from the claim text.