Interface built in test failure detection apparatus
AssigneeRaytheon Company
InventorsMicky Harris, Magathi J. Willis
Life of this patent
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Abstract
An interface BIT failure detection circuit includes a sequencing circuit and a multiplexer. The sequencing circuit configured to generate the sequence selection signal. The multiplexer is in signal communication with the sequencing circuit, and includes a plurality of interface input. Each interface input corresponds to an interface of a device under test. The sequence selection signal is configured to control the MUX to sequentially select each of the interface inputs. The MUX includes an output terminal configured to output a test signal configured to indicate whether or not at least one fault corresponding to one or more of the interface inputs or a main power supply exists.
Claims20
An interface built-in test (BIT) failure detection circuit comprising:
- a sequencing circuit configured to generate a sequence selection signal,
- a multiplexer (MUX) in signal communication with the sequencing circuit, the MUX including a plurality of interface inputs, each interface input corresponding to an interface of a device under test (DUT),
- wherein the sequence selection signal is configured to control the MUX to sequentially select each of the interface inputs, and
- wherein the MUX includes an output terminal configured to output a test signal configured to indicate whether or not at least one fault corresponding to one or more of the interface inputs or a main power supply exists.
A method of controlling an interface built-in test (BIT) failure detection circuit comprising:
- generating, by a sequencing circuit, a sequence selection signal;
- delivering the sequence selection signal to a multiplexer (MUX) that includes a plurality of interface inputs, each interface input corresponding to an interface of a device under test (DUT);
- controlling the MUX to sequentially select each of the interface inputs in response to the sequence selection signal;
- and
- outputting, from an output terminal of the MUX, a test signal indicating whether at least one fault corresponding to one or more of the interface inputs or a main power supply exists.
Dependencies are inferred from the claim text.