Back to results
US 2025/0016119 A1Published application
Network interface and buffer control method thereof
AssigneeHitachi Vantara, Ltd.
InventorsNobuhiro YOKOI, Hiroka IHARA
Life of this patent
Estimating the term…
Abstract
A network interface includes a processor, memory, and a cache between the processor and the memory. The processor secures a plurality of buffers for storing transfer data in the memory, and manages an allocation order of available buffers of the plurality of buffers. The processor returns a buffer released after data transfer to a position before a predetermined position of the allocation order.
Claims9
A network interface comprising:
- a processor;
- a memory;
- and
- a cache accessed by the processor prior to accessing the memory, wherein
- the processor is configured to
- secure a plurality of buffers for storing transfer data in the memory,
- manage an allocation order of available buffers of the plurality of buffers,
- return a buffer released after data transfer to a head position of the allocation order as an available buffer, and
- use the available buffers for data transfer from the available buffer at the head position.
6 more elements
A buffer control method in a network interface including a processor, a memory, and a cache accessed by the processor prior to the memory, the buffer control method comprising:
- by the processor,
- securing a plurality of buffers for storing transfer data in the memory;
- managing an allocation order of available buffers of the plurality of buffers;
- returning a buffer released after data transfer to a head position of the allocation order as an available buffer;
- and
- use the available buffers for data transfer from the available buffer at the head position.
3 more elements
Dependencies are inferred from the claim text.