Encoding method, decoding method, encoding circuit and decoding circuit for single-channel communication

An encoding circuit for single-channel communication, comprising:

• a first delay circuit configured to generate a first delay clock signal based on a clock signal;
• a pulse generator configured to generate a pulse signal based on the first delay clock signal;
• a long-code flip-flop, which has a reset terminal for receiving the pulse signal and outputting a high level of a long-code signal, and has a clock terminal for receiving the clock signal, the clock signal triggering an output of a low level of a long-code signal;
• a short-code flip-flop, which has a reset terminal for receiving the pulse signal and outputting a high level of a short-code signal;
• a second delay circuit configured to generate a second delay clock signal based on the first delay clock signal,
• a clock terminal of the short-code flip-flop for receiving the second delay clock signal and outputting a low level of the short-code signal;
• a selection flip-flop, which has a clock terminal for receiving the first delay clock signal, a data terminal coupled to a data signal, and an output terminal for outputting a data delay signal;
• and
• a data selector, which has a first input terminal coupled to an output terminal of the long-code flip-flop, a second input terminal coupled to an output terminal of the short-code flip-flop, and a selection terminal coupled to the output terminal of the selection flip-flop, the data selector selecting and outputting the long-code signal or the short-code signal based on the data delay signal to form a long- and short-code signal.

An encoding circuit for single-channel communication, comprising:

• a first delay circuit configured to generate a first delay clock signal based on a clock signal;
• a second delay circuit configured to generate a second delay clock signal based on the first delay clock signal;
• a first pulse generator configured to generate a first pulse signal based on the first delay clock signal;
• a second pulse generator configured to generate a second pulse signal based on the second delay clock signal;
• a third pulse generator configured to generate a third pulse signal based on the first delay clock signal;
• a selection flip-flop, which has a clock terminal for receiving the first delay clock signal, a data terminal coupled to a data signal, and an output terminal for outputting a data delay signal;
• a data selector, which has a first input terminal coupled to the first pulse generator, a second input terminal coupled to the second pulse generator, and a selection terminal coupled to the data delay signal and selecting the first pulse signal or the second pulse signal based on the data delay signal;
• and
• an output flip-flop, which has a reset terminal coupled to the third pulse generator, and a clock terminal coupled to an output terminal of the data selector, wherein the output flip-flop generates a high level of a long-code signal or a high level of a short-code signal based on the third pulse signal, the clock terminal receives the first pulse signal and generates a low level of the long-code signal, and the clock terminal receives the second pulse signal and generates a low level of the short-code signal.

A decoding method for single-channel communication, comprising:

• generating a low level of a clock signal based on a high level of a long- and short-code signal;
• generating a delay pulse signal based on the long- and short-code signal, a delay time length of the delay pulse signal being a half of a clock period;
• generating a high level of the clock signal based on the delay pulse signal;
• and
• generating a digital signal based on the clock signal and the long- and short-code signal.

A decoding circuit for single-channel communication, comprising:

• a delay pulse circuit configured to delay a long- and short-code signal by half a clock period and generate a long- and short-code delay signal;
• a pulse generator configured to generate a delay pulse signal based on the long- and short-code delay signal;
• a clock flip-flop, which has a clock terminal coupled to the long- and short-code signal and generating a low level of a clock signal based on the long- and short-code signal, and a reset terminal coupled to an output terminal of the pulse generator, the clock flip-flop generating a high level of the clock signal based on the delay pulse signal;
• and
• a digital signal flip-flop, which has a clock terminal coupled to an output terminal of the clock flip-flop, and a data terminal coupled to the long- and short-code signal, the digital signal flip-flop generating a digital high level or a digital low level based on the clock signal.