Performance Optimization for Storing Data in Memory Services Configured on Storage Capacity of a Data Storage Device
AssigneeMicron Technology, Inc.
InventorLuca BERT
Life of this patent
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AssigneeMicron Technology, Inc.
InventorLuca BERT
Estimating the term…
Techniques to improve performance of storing data to memory addresses implemented in a storage capacity of a memory sub-system. A connection from the memory sub-system to a host system supports both a protocol for cache-coherent memory access to a memory device implemented in the storage capacity and a protocol for storage access. The memory sub-system can use a cache memory to cache pages of the memory device for accessing over the connection. A storage access queue can be configured to provide a command configured to store data at a memory address in the memory device. Such commands can be entered in the queue when the cache memory is temporarily unavailable, or to cause the memory sub-system to swap a cached page from the cache memory to the storage capacity.
A method, comprising:
A memory sub-system, comprising:
A non-transitory computer storage medium storing instructions which, when executed in a computing system, cause the computing system to perform a method, comprising:
Dependencies are inferred from the claim text.