Decoders, decoding methods, memory controllers and memory systems
AssigneeYangtze Memory Technologies Co., Ltd.
InventorsHua Tan, ChuangChuang Zhao
Life of this patent
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AssigneeYangtze Memory Technologies Co., Ltd.
InventorsHua Tan, ChuangChuang Zhao
Estimating the term…
The present disclosure provides a decoder including: a check node updating circuit and a variable node updating circuit. In a first time period, these circuits obtain the check node messages corresponding to different layers of the check matrix in the first updating units of different levels in the first updating units of a levels and obtain corresponding intermediate calculation values in the second updating units of different levels in the second updating units of a levels. After, the second updating units sequentially receive the check node messages corresponding to each layer of the check matrix and calculate the received check node messages with the intermediate calculation values of the second updating unit of the next level. From this, they obtain the variable node messages corresponding to different columns of the check matrix in the second updating units of different levels in the second updating units of a levels.
A decoder, wherein a check matrix corresponding to a frame of code words comprises a*a sub-matrices, a plurality of sub-matrices located in the same row in the check matrix constitute a layer of the check matrix, and a plurality of sub-matrices located in the same column constitute a column of the check matrix, the decoder comprising:
A memory system comprising:
A decoding method, wherein during decoding a frame of code words with a check matrix including a*a sub-matrices, a plurality of sub-matrices located in the same row in the check matrix constitute a layer of the check matrix, and a plurality of sub-matrices located in the same column constitute a column of the check matrix, the method comprising:
Dependencies are inferred from the claim text.