Memory circuit comprising electronic cells and a control circuit
AssigneeSTMicroelectronics International N.V.
InventorAndrea REDAELLI
Life of this patent
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Abstract
A memory circuit includes a memory array formed by electronic cells. Each electronic cell includes an integrated stack having, successively, a first electrode, an intermediate layer formed by an ovonic threshold switching layer, and a resistor connected to the intermediate layer. A control circuit is connected to the electronic cell. The control circuit is structured and configured to apply, between the first electrode and the resistor, a first voltage impulse of a first polarity to set a first logic state of the electronic cell and a second voltage impulse of a second polarity, opposite the first polarity, to set a second logic state of the electronic cell.
Claims18
A memory circuit, comprising:
- a memory array comprising a plurality of electronic cells, wherein at least one electronic cell comprises an integrated stack having successively:
- i) a first electrode;
- ii) an intermediate layer comprising an ovonic threshold switching layer;
- and
- iii) a resistor connected to the intermediate layer;
- and
- a control circuit connected to the at least one electronic cell, wherein the control circuit is configured to apply, between the first electrode and the resistor, a first voltage impulse of a first polarity to set a first logic state of the electronic cell and apply a second voltage impulse of a second polarity, opposite the first polarity, to set a second logic state, different from the first logic state, of the electronic cell.
A circuit, comprising:
- an ovonic threshold switching memory cell formed by an integrated stack comprising a first electrode, a resistor, and an ovonic threshold switching layer having a first surface in contact with the first electrode and a second surface in contact with the resistor;
- and
- a control circuit electrically connected to the ovonic threshold switching memory cell and configured to set a first logic state by applying, between the first electrode and the resistor, a first voltage impulse of a first polarity and to set a second logic state, different than the first logic state, by applying, between the first electrode and the resistor, a second voltage impulse of a second polarity opposite the first polarity.
Dependencies are inferred from the claim text.