Charge domain digital, generative pre-trained transformer (gpt) and digital storage

A NAND ID and Transfer Logic Gate (ITGL) comprising:

• an input diode coupled to a first control input;
• a transfer gate coupled to a second control input;
• an output memory node;
• wherein an input diode potential is below a minimum potential of the output memory node when the first control input is high, wherein the transfer gate blocks conduction when the second control input is low, such that only when a potential minimum of the input diode is raised and a barrier is lowered can charge move to the output memory node.

A charge domain shift register, comprising:

• a plurality of charge storage elements;
• a plurality of transfer gates separating the plurality of charge storage elements;
• and
• control inputs coupled to each of the plurality of transfer gates for controlling a depletion potential level under said transfer gates to erect or remove barriers;
• wherein the plurality of charge storage elements and the plurality of transfer gates are fabricated on a fin.

A charge domain shift register, comprising:

• a source of charge;
• a plurality of charge storage elements;
• an output charge storage element coupled to the plurality of charge storage elements;
• a plurality of notch type transfer gates separating the plurality of charge storage elements;
• and
• control inputs coupled to the plurality of notch type transfer gates;
• wherein a charge is moved through the charge domain shift register by clocking the control inputs.

A logic circuit implementing XNOR functionality, comprising:

• at least two sources of charge;
• a summing memory node;
• notch gates coupling the two sources of charge to the summing node;
• a carry memory node coupled through a fixed barrier to the summing node, wherein a fixed barrier potential height is set relative to a summing node potential such that if all inputs to the summing node are high then charge transfers to the carry memory node over the fixed barrier, but if less than all inputs to the summing node are high then charge transfer to the summing node does not transfer to the carry memory node;
• and
• a sense gate coupled to the carry memory node, wherein the sense gate further actuates a sink when charge is detected on the carry memory node, and wherein the sink is coupled to the summing memory node to remove the charge from the summing memory node in conformance with a signal from the sense gate.

A series to parallel converter, comprising:

• an input source of charge;
• a plurality of charge based shift registers, wherein a first charge based shift register coupled to the input source of charge, a remaining plurality of charge based shift registers orientated at an angle to each element of the first charge based shift register;
• an output charge storage element coupled to each of the remaining plurality of shift registers;
• wherein the first shift register accept series information from the input source of charge and provide the series information as parallel.

A parallel to series converter comprising:

• a plurality input charge sources;
• a charge based shift register at an angle to said plurality of input charge sources whose series elements are coupled to said plurality of input charge sources, wherein charge is loaded to the series elements of the charge based shift register according to a number of input sources and then shifted by the number of input sources;
• and
• an output charge storage element coupled to the shift register;
• wherein the output charge element provides the serialized output of the parallel inputs.

A serdes, comprising:

• a series to parallel converter, comprising:
• an input source of charge;
• a plurality of charge based shift registers, wherein a first charge based shift register coupled to the input source of charge, a remaining plurality of charge based shift registers orientated at an angle to each element of the first charge based shift register;
• an output charge storage element coupled to each of the remaining plurality of shift registers;
• wherein the first shift register accepts series information from the input source of charge and provide the series information as parallel;
• a pair of notch transfer gates separating sources of charge from a memory node;
• wherein the notch transfer gates can one of move or remove charge from the memory node;
• wherein the memory node is coupled to a sense gate which is coupled to a control node of a VCO used in the serdes.

A field programmable gate array, comprising:

• charge domain logic (CDL) functions coupled to a plurality of charge based shift registers where sense gates may be selected to choose the output of each gate desired;
• an input map corresponding to desired logic functions;
• and
• a multiplexer coupling the input map to sense gates to the shift registers and said shift registers to each other so as to produce a succession of logic functions.

A circuit to set a depth of a notch gate, comprising:

• a charge storage memory node;
• a charge domain notch gate coupled to the charge storage memory node;
• two capacitors connecting in series;
• a first current source coupled between a supply and a non-shared terminal of a first capacitor of the two capacitors;
• a second current source coupled to a shared terminal of the two capacitors and ground or supply;
• a third current source coupled to the non-shared terminal of the second capacitor;
• a first switch connected between the non-shared terminal of the first capacitor and ground;
• a second switch connected between the shared terminal of the two capacitors and ground;
• a comparator connected to the shared terminal of the two capacitors on one terminal and ground on the other, the comparator coupled to actuate the second and third current sources when the shared terminal potential of the two capacitors is below ground;
• and
• a notch gate controlling the notch depth coupled to a non-shared terminal of the second capacitor and the transfer gate portion of the notch gate coupled to the shared terminal.

A VCO control register, comprising:

• a source of input charge;
• a first charge based memory node coupled to the source of input charge by a notch gate;
• a second charge based memory node whose charge level is set below the minimum potential of said first charge based memory node or a sink or a diode set below said minimum potential coupled to the first charge based memory node by a notch gate;
• and
• a sense gate coupled to the first charge based memory node and an oscillator voltage based frequency control register;
• wherein the oscillator frequency is regulated by control inputs which actuate the transferring of charge into and out of the first memory node to increase and decrease the voltage of the voltage based frequency control register.

A multiply and add circuit, comprising:

• a source of charge;
• an output memory node;
• a memory node coupled by notch gates between said source of charge and said output memory node;
• a control means coupled to said notch gates for controlling notch depth;
• and
• a capacitor formed by a vertical dielectric separating the third MN from a thyristor;
• said thyristor striking when the rate of change of the final MN exceeds a threshold whose output is further coupled to said control means;
• where data input is a number of cycles the gate is actuated by said control means and;
• where weights are the depth of the notch.

A timer comprising:

• a source of charge;
• an output memory node;
• one or more memory nodes coupled by notch gates between said source of charge and said output memory node;
• a control means coupled to said notch gates for controlling notch depth;
• a capacitor formed by a vertical dielectric separating the output memory node from a thyristor;
• said thyristor striking when the rate of change of the output memory node exceeds a threshold whose output is further coupled to said control means;
• where the depth of each notch sets the number of actuations required to fill each memory node in turn and;
• all memory nodes being full is indicated when the thyristor no longer actuates because charge cannot be transferred into the output memory node to produce a potential change to couple through the capacitor to the thyristor.

A replicator, comprising:

• an input charge memory node;
• and
• a sense gate coupled to said input charge memory node;
• an input diode coupled to one side of a transfer gate capable of actuating a barrier;
• wherein said sense gate further coupled to the control gate of said transfer gate barrier;
• an output charge memory node further coupled to said transfer gate barrier;
• wherein movement of charge to said sense gate from said input memory node raises the potential of said transfer gate erecting a barrier proportional in height to the input charge and;
• wherein said input diode actuated so as to fill the output memory node with a charge coincident with the height of said barrier, by raising the charge level above and then the input diode charge level lowered by said barrier height, where said charge on said output memory node can be used and replenished by repeating the actuation of said input diode such that the output charge remains can be restored each cycle in proportion to the charge initially on the input charge memory node.