US 2024/0407158 A1 · INTEGRATED CIRCUIT DEVICE

Abstract

The inventive concept provides an integrated circuit device including: a substrate including a cell region and a peripheral circuit region; a plurality of bit line structures spaced apart from each other in the cell region with each bit line structure including a bit line conductive layer and a bit line capping layer on the bit line conductive layer; and a plurality of landing pads with each landing pad of the plurality of landing pads disposed on a respective bit line structure of the plurality of bit line structures and electrically connected to the substrate, wherein the peripheral circuit region includes a gate structure and a core capping layer on the gate structure; a direct contact plug extending vertically with respect to the substrate; first peripheral circuit wiring patterns extending laterally and spaced apart from each other on a first plane at a first vertical level relative to the substrate; and second peripheral circuit wiring patterns extending laterally and spaced apart from each other on a second plane at a second vertical level relative to the substrate, wherein the second vertical level is different from the first vertical level.

Claims20

Dependent claims

An integrated circuit device comprising:

a substrate comprising a cell region and a peripheral circuit region;
a plurality of bit line structures spaced apart from each other in the cell region with each bit line structure comprising a bit line conductive layer and a bit line capping layer on the bit line conductive layer;
and
a plurality of landing pads with each landing pad of the plurality of landing pads disposed on a respective bit line structure of the plurality of bit line structures and electrically connected to the respective bit line structure,
wherein the peripheral circuit region comprises a gate structure and a core capping layer on the gate structure;
a direct contact plug extending vertically with respect to the substrate;
first peripheral circuit wiring patterns extending laterally and spaced apart from each other on a first plane at a first vertical level relative to the substrate;
and
second peripheral circuit wiring patterns extending laterally and spaced apart from each other on a second plane at a second vertical level relative to the substrate, wherein the second vertical level is different from the first vertical level.

6 more elements

Dependencies are inferred from the claim text.

Integrated circuit device

Life of this patent

Integrated circuit device

Life of this patent

Abstract

Claims20