Semiconductor memory device and manufacturing method thereof
AssigneeNanya Technology Corporation
InventorsKai-Po SHANG, Wei-Ming LIAO
Life of this patent
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Abstract
A semiconductor memory device includes a substrate with an active area, a bit line contact in contact with the active area, and a bit line having an end portion in contact with the bit line contact, wherein the end portion has a first trapezoidal profile. A semiconductor memory device manufacturing method is also disclosed to utilize a vertical etching process which has an etching recipe to have higher conductive material/barrier layer selectivity, thereby enlarging bit line contact to active area landing area and improving a contact resistance of the bit line contact.
Claims15
A semiconductor memory device comprising:
- a substrate comprising an active area;
- a bit line contact in contact with the active area;
- and
- a bit line having an end portion in contact with the bit line contact, wherein the end portion has a first trapezoidal profile.
A semiconductor memory device manufacturing method comprising:
- providing a substrate with an active area;
- forming a bit line contact in the active area;
- forming a bit line having an end portion in contact with the bit line contact, wherein the end portion of the bit line comprises a metal conductive portion and at least one barrier layer;
- and
- etching the bit line and the bit line contact by an etching recipe that has a higher etching rate to the metal conductive portion and a lower etching rate to the at least one barrier layer.
Dependencies are inferred from the claim text.