Memory device and forming method thereof
AssigneeNanya Technology Corporation
InventorsKuo Chung HSU, En-Jui LI
Life of this patent
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Abstract
The present disclosure provides a memory device and the forming method thereof. The memory device includes a bit line on a substrate, a multilayer spacer covering the bit line, a low-k dielectric layer and an air gap interposed in the multilayer spacer, and a cell contact adjacent to the multilayer spacer. The multilayer spacer, the low-k dielectric layer, and the air gap are disposed between the bit line and the cell contact. The top surface of the low-k dielectric layer is lower than a top surface of the bit line. The air gap is above the low-k dielectric layer, and an orthogonal projection of the air gap onto the substrate is partially overlapped with that of the low-k dielectric layer onto the substrate.
Claims20
A memory device, comprising:
- a bit line on a substrate;
- a multilayer spacer covering the bit line;
- a low-k dielectric layer interposed in the multilayer spacer, wherein a top surface of the low-k dielectric layer is lower than a top surface of the bit line;
- an air gap interposed in the multilayer spacer, wherein the air gap is above the low-k dielectric layer, and an orthogonal projection of the air gap onto the substrate is partially overlapped with that of the low-k dielectric layer onto the substrate;
- and
- a cell contact adjacent to the multilayer spacer, wherein the multilayer spacer, the low-k dielectric layer, and the air gap are disposed between the bit line and the cell contact.
A method of forming a memory device, comprising:
- forming a first spacer layer covering a bit line on a substrate;
- forming a low-k dielectric layer on a sidewall of the first spacer layer, wherein a top surface of the low-k dielectric layer is lower than a top surface of the bit line;
- forming a second spacer layer covering the low-k dielectric layer and the first spacer layer;
- forming a sacrificial layer on a sidewall of the second spacer layer, wherein the sacrificial layer is above the low-k dielectric layer, and an orthogonal projection of the sacrificial layer onto the substrate is partially overlapped with that of the low-k dielectric layer onto the substrate;
- forming a third spacer layer covering the sacrificial layer and the second spacer layer;
- forming a cell contact adjacent to the third spacer layer;
- and
- removing the sacrificial layer to form an air gap between the second spacer layer and the third spacer layer.
Dependencies are inferred from the claim text.