Memory cell circuit, memory cell array structure and manufacturing method thereof
AssigneeMacronix International Co., Ltd.
InventorsWei-Chen Chen, Hang-Ting Lue
Life of this patent
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Abstract
A memory cell circuit, a memory cell array structure and a manufacturing method thereof are provided. The memory cell circuit includes a first transistor, a second transistor and a capacitor. The first transistor has a first end electrically coupled to a bit line, and a gate of the first transistor is electrically coupled to a primary word line. The second transistor has a first end electrically coupled to a second end of the first transistor, and a gate of the second transistor is electrically coupled to an auxiliary word line. A first end of the capacitor is electrically coupled to a second end of the second transistor and a second end of the capacitor receives a reference voltage.
Claims26
A memory cell circuit, comprising:
- a first transistor, having a first end electrically coupled to a bit line, wherein a gate of the first transistor is electrically coupled to a primary word line;
- a second transistor, having has a first end electrically coupled to a second end of the first transistor, wherein a gate of the second transistor is electrically coupled to an auxiliary word line;
- and
- a capacitor, having an end electrically coupled to a second end of the second transistor, wherein another end of the capacitor receives a reference voltage.
A memory cell array structure, comprising:
- a plurality of channel pillars, arranged in an array to form a plurality of channel pillar rows and a plurality of channel pillar columns;
- a plurality of first conductive structures, respectively electrically coupled to the channel pillar rows or the channel pillar columns, and each of the first conductive structures surrounding a first portion of the channel pillars in each of the channel pillar rows or each of the channel pillar columns, wherein each of the first conductive structures forms a common gate of a plurality of first transistors in each of the channel pillar rows or each of the channel pillar columns;
- at least one second conductive structure, respectively electrically coupled to the channel pillar rows or the channel pillar columns, and each of the second conductive structure surrounding a second portion of the channel pillars in each of the channel pillar rows or each of the channel pillar columns, wherein each of the second conductive structures forms a common gate of a plurality of second transistors in each of the channel pillar rows or each of the channel pillar columns, wherein there is a spacing distance between the first portion and the second portion;
- and
- a plurality of capacitors, respectively electrically coupled to end portions of channel pillars adjacent to the second conductive structures.
A manufacturing method of a memory cell array structure, comprising:
- forming a plurality of channels on a wafer, wherein the wafer has a plurality of channel layers and a plurality of sacrifice layers stacked alternately;
- masking a gate region of the wafer, removing the sacrifice layers in a source region and a drain region of the wafer, to respectively form a plurality of source structures and a plurality of drain structures;
- masking the source region and the drain region of the wafer, and dividing the gate region into a first division and a second division;
- and
- respectively forming a plurality of first conductive structures and at least one second conductive structure in the first division and the second division, wherein each of the first conductive structures is a first common gate of a plurality of a plurality of first transistors, and each of the second conductive structure is a second common gate of a plurality of second transistors.
Dependencies are inferred from the claim text.