Methods of manufacturing semiconductor device

A semiconductor device comprising:

• a first cell source/drain region, a second cell source/drain region, and a cell gate including a cell transistor;
• a first peripheral source/drain region, a second peripheral source/drain region, and a peripheral gate including a peripheral transistor;
• a bit line electrically connected to the first cell source/drain region;
• a cell conductive structure electrically connected to the second cell source/drain region;
• a peripheral conductive structure electrically connected to the first peripheral source/drain region;
• and
• a data storage structure electrically connected to the cell conductive structure,
• wherein the cell conductive structure includes:
• a cell contact portion on the second cell source/drain region;
• and
• a cell pad portion on the cell contact portion,
• wherein the peripheral conductive structure includes:
• a peripheral contact portion on the first peripheral source/drain region;
• and
• a peripheral wiring portion on the peripheral contact portion,
• wherein, in a plan view, the cell pad portion includes:
• a first side and a second side opposing each other in a first direction;
• a third side and a fourth side opposing each other in a second direction different from the first direction;
• a first rounded corner where a first side and the fourth side meet;
• a second rounded corner where a first side and the third side meet;
• a third rounded corner where a second side and the third side meet;
• and
• a fourth rounded corner where a second side and the fourth side meet,
• wherein the peripheral wiring portion has a line shape extending in a third direction, and
• wherein the third direction is different from the first direction and the second direction.

A semiconductor device comprising:

• a first cell source/drain region, a second cell source/drain region, and a cell gate including a cell transistor;
• a bit line electrically connected to the first cell source/drain region;
• a cell conductive structure electrically connected to the second cell source/drain region;
• and
• a data storage structure electrically connected to the cell conductive structure,
• wherein the cell conductive structure includes:
• a cell contact plug on the second cell source/drain region;
• and
• a cell pad pattern on the cell contact plug,
• wherein, in a plan view, the cell pad pattern includes:
• a first side and a second side opposing each other in a first direction;
• a third side and a fourth side opposing each other in a second direction different from the first direction;
• a first rounded corner where a first side and the fourth side meet;
• a second rounded corner where a first side and the third side meet;
• a third rounded corner where a second side and the third side meet;
• and
• a fourth rounded corner where a second side and the fourth side meet,
• wherein the first rounded corner and the third rounded corner oppose each other in a third direction,
• wherein the second rounded corner and the fourth rounded corner oppose each other in a fourth direction perpendicular to the third direction, and
• wherein the bit line has a line shape extending in the third direction.