Real Time Stream Camera ISP With Loosely Coupled Control Loop

A system-on-chip (SoC), comprising:

• a configuration register memory that stores one or more synchronization settings;
• a first processing circuit that configures the configuration register memory with the one or more synchronization settings;
• a first camera image frame processing circuit connected to an input camera to receive and process first and second camera image frame sequences having, respectively, first and second specified exposures;
• and
• an image signal processing (ISP) pipeline that is connected and configured:
• to process, in response to a first synchronization setting having a first value, the first and second camera image frame sequences to detect a set of complete frames from the first and second camera image frame sequences which have a first common frame number;
• to identify a valid combination of different exposures from the first and second camera image frame sequences having a second common frame number succeeding the first common frame number;
• and
• to process the valid combination of different exposures from the first and second camera image frame sequences to generate output data from the ISP pipeline.

A real-time stream camera image signal processing system, comprising:

• a memory device to store a dual exposure VSYNCH lock (DEVL) synchronization setting and a single step enable (SSEN) synchronization setting;
• a real-time camera stream pipeline hardware circuit that is connected and configured to receive and process first and second camera image frame sequences having, respectively, first and second specified exposures;
• and
• an autoexposure control unit coupled to the memory device and connected with the real-time camera stream pipeline hardware circuit;
• where the real-time camera stream pipeline hardware circuit is connected and configured:
• to process, in response to the DEVL synchronization setting having a first value, the first and second camera image frame sequences to detect a set of complete frames which have a first common frame number;
• to identify a valid combination of different exposures from the first and second camera image frame sequences having a second common frame number succeeding the first common frame number;
• and
• to process the valid combination of different exposures from the first and second camera image frame sequences to generate output data from the real-time camera stream pipeline hardware circuit.