High-side transistor partitioning and control
AssigneeTexas Instruments Incorporated
InventorsTaisuke KAZAMA, Mustapha EL-MARKHI, Indumini W RANMUTHU
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Abstract
A circuit includes a transistor, a first driver, a second driver, and a delay circuit. The transistor includes an array of transistor cells partitioned into a first switch and a second switch. The first driver is configured to control the first switch. The second driver is configured to control the second switch. The delay circuit is coupled between the first driver and the second driver. The delay circuit is configured to delay closure of the second switch until the first switch is closed and a voltage across the first switch is less than a predetermined voltage.
Claims20
A circuit comprising:
- a transistor including an array of transistor cells partitioned into a first switch and a second switch, the first switch having a first control input and the second switch having a second control input;
- a first driver having a first driver input and a first driver output, the first driver output coupled to the first control input;
- and
- a second driver having a second driver input and second driver output, the second driver output coupled to the second control input;
- and
- a delay circuit coupled between the first driver input and the second driver input.
A circuit comprising:
- a transistor including an array of transistor cells partitioned into a first switch and a second switch;
- a first driver configured to control the first switch;
- a second driver configured to control the second switch;
- and
- a delay circuit coupled between the first driver and the second driver, the delay circuit configured to delay closure of the second switch until the first switch is closed and a voltage across the first switch is less than a predetermined voltage.
A switching converter comprising:
- a high-side transistor including an array of transistor cells partitioned into a first switch and a second switch, the first switch having a first control input and a first current terminal, and the second switch having a second control input and a second current terminal;
- a low-side transistor including a third control input, and a third current terminal coupled to the first current terminal and the second current terminal;
- a first driver having a first driver input and a first driver output, the first driver output coupled to the first control input;
- and
- a second driver having a second driver input and second driver output, the second driver output coupled to the second control input;
- a third driver having a third driver output coupled to the third control input;
- and
- a delay circuit coupled between the first driver input and the second driver input.
Dependencies are inferred from the claim text.