US 2024/0405698 A1 · METHOD FOR DC-BUS CAPACITANCE MINIMIZATION OF HYBRID CLAMPED CONVERTER

Abstract

The present invention provides a method for DC-bus capacitance minimization of hybrid clamped converter (HCC), which includes: obtaining the system parameters of the HCC during operation; determining the reference wave; determining the duty ratio of each switch according to the reference wave; determining the total neutral point current of the system; the fundamental component of the upper and lower DC-bus capacitor voltage of the system; determining the maximum voltage fluctuation of the upper and lower DC-bus capacitors; determining the minimum DC-bus capacitance value that satisfies the requirements of system capacitor voltage fluctuation by traversing the capacitance value. The present invention not only reduces the design complexity and cost of the high-power HCC system, but also improves the power density and reliability of the converter.

A method for DC-bus capacitance minimization of hybrid clamped converter, including the following steps:

step 1:
obtaining a DC-bus voltage Vdc, a reference wave frequency fac, a carrier frequency fc, a modulation ratio ma, a power factor cos φ, a load impedance Z, and a system capacitor voltage fluctuation limit ΔVlimit when the HCC is operating;
step 2:
determining a reference wave V′ref_x:
V
ref
⁢
_
⁢
x
′
=
V
ref
⁢
_
⁢
x
+
V
com
=
{
V
ref
⁢
_
⁢
a
+
V
com
=
m
a
2
⁢
sin
⁡
(
2
⁢
π
⁢
f
ac
⁢
t
)
+
0.5
+
V
com
V
ref
⁢
_
⁢
b
+
V
com
=
m
a
2
⁢
sin
⁡
(
2
⁢
π
⁢
f
ac
⁢
t
-
2
⁢
π
3
)
+
0.5
+
V
com
V
ref
⁢
_
⁢
c
+
V
com
=
m
a
2
⁢
sin
⁡
(
2
⁢
π
⁢
f
ac
⁢
t
-
2
⁢
π
3
)
+
0.5
+
V
com
where, Vref_x takes Vref_a, Vref_b, Vref_c, Vref_a, Vref_b, and Vref_c denote a reference wave of a-phase, b-phase, and c-phase, respectively;
Vcom denotes a common-mode voltage;
step 3:
determining a switch duty ratio DNx of HCC according to the reference wave V′ref_x:
D
Nx
=
f
⁡
(
V
ref
⁢
_
⁢
x
′
)
=
{
2
⁢
V
ref
⁢
_
⁢
x
′
0
≤
V
ref
⁢
_
⁢
x
′
≤
1
/
3
2
/
3
1
/
3
≤
V
ref
⁢
_
⁢
x
′
≤
2
/
3
2
⁢
(
1
-
V
ref
⁢
_
⁢
x
′
)
2
/
3
≤
V
ref
⁢
_
⁢
x
′
≤
1
step 4:
determining a total neutral point current in of the system according to the switch duty ratio DNx and a load current iox:
i
N
=
D
Na
⁢

i
oa
+
D
Nb
⁢

i
ob
+
D
Nc
⁢

i
oc
where DNx denotes a switch duty ratio of a-phase, b-phase or c-phase;
DNa denotes the switch duty ratio of a-phase;
DNb denotes the switch duty ratio of b-phase;
DNc denotes the switch duty ratio of the c-phase;
iox denotes the load current of a-phase, b-phase or c-phase;
ioa denotes the load current of a-phase;
iob denotes the load current of b-phase;
ioc denotes the load current of c-phase;
step 5:
determining a fundamental component Vcap of the capacitors voltage of the upper and lower DC-bus of the system according to the total neutral point current iN of the system:
V
cap
=
∫
0
t
i
N
⁢
dt
C
d
⁢
1
where Cd1 denotes a value of the DC-bus capacitance to be determined, the DC-bus capacitors are divided into three DC-bus capacitors:
upper, middle, and lower, and the three capacitance values are equal;
step 6:
determining a maximum voltage fluctuation ΔVcd1/cd3_max of upper and lower DC-bus capacitors according to Vcap:
Δ
⁢
V
cd
⁢
1
/
cd
⁢
3
⁢
_
⁢
max
=
Δ
⁢
V
cd
⁢
1
/
cd
⁢
3
⁢
_
⁢
f
⁢
_
⁢
max
+
Δ
⁢
V
cd
⁢
1
/
cd
⁢
3
⁢
_
⁢
h
⁢
_
⁢
max
=
max
⁡
(
V
cap
)
-
min
⁡
(
V
cap
)
2
+
3
⁢
Δ
⁢
V
cd
⁢
2
⁢
_
⁢
max
where ΔVcd1/cd3_f_max is the fundamental component of the maximum voltage fluctuation of the upper and lower DC-bus capacitors;
ΔVcd1/cd3_h_max is a harmonic component of the maximum voltage fluctuation of the upper and lower DC-bus capacitors;
max(Vcap) is a maximum value of the fundamental component of the upper and lower DC-bus capacitors voltage, and min(Vcap) is a minimum value of the fundamental component of the upper and lower DC-bus capacitors voltage;
ΔVcd2_max is a maximum voltage fluctuation of the middle DC-bus capacitor;
step 7:
traversing the capacitance value Cd1 from 0 to Cmax, a step length of the traversal is M1, repeating the above-mentioned steps 1-6 to obtain the corresponding ΔVcd1/cd3_max of different capacitance values, and when the ΔVcd1/cd3_max is less than or equal to ΔVlimit for the first time, outputting the corresponding capacitance value, that is, a minimum DC-bus capacitance value satisfying the requirement of system capacitor voltage fluctuation.

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Method for dc-bus capacitance minimization of hybrid clamped converter

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Method for dc-bus capacitance minimization of hybrid clamped converter

Life of this patent

Abstract

Claims8