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US 2024/0405133 A1Published application
Optical semiconductor device with cascade vias
AssigneeNanya Technology Corporation
InventorMING-HUNG HSIEH
Life of this patent
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Abstract
An optical semiconductor device with cascade vias is disclosed. The semiconductor device a logic die having a core circuit area and a logic peripheral circuit area; a memory die positioned on the logic die and having a memory cell area and a memory peripheral area; a first inter-die via positioned in the memory peripheral area; a landing pad positioned on the first inter-die via; and a sensor die positioned on the memory die and including a sensor pixel area and a sensor peripheral area, a first intra-die via positioned in the sensor peripheral area. The first inter-die via and the first intra-die via are electrically coupled through the landing pad in a cascade manner.
Claims12
1:
- A semiconductor device, comprising:
- a logic die comprising:
- a core circuit area and a logic peripheral circuit area;
- a memory die positioned on the logic die and comprising:
- a memory cell area and a memory peripheral area;
- a first inter-die via positioned in the memory peripheral area, wherein the first inter-die via has a back end extended to a back surface of the memory die and a front end extended through a front surface of the memory die;
- a landing pad positioned on the first inter-die via;
- and
- a sensor die positioned on the memory die and comprising:
- a sensor pixel area and a sensor peripheral area;
- a first intra-die via positioned in the sensor peripheral area, wherein the first intra-die via has a back end extended to a back surface of the sensor die and a front end extended to a front surface of the sensor die;
- wherein the landing pad has a front surface in contact with the back surface of the memory die and a back surface in contact with the front surface of the sensor die;
- wherein the first inter-die via and the first intra-die via are electrically coupled through the landing pad in a cascade manner;
- wherein the first inter-die via and the first intra-die via are not topographically aligned;
- wherein the first inter-die via is electrically connected to the logic peripheral circuit area and the memory peripheral area.
12 more elements
2:
- The semiconductor device of claim 1, wherein the back end of the first inter-die via is in contact with the front surface of the landing pad while the front end of the first intra-die via is in contact with the back surface of the landing pad.
3:
- The semiconductor device of claim 2, wherein the sensor die comprises:
- a dielectric layer of the sensor die;
- a substrate positioned on the dielectric layer of the sensor die;
- and
- a sensor unit positioned in the substrate of the sensor die;
- wherein the first inter-die via is electrically connected to the logic peripheral circuit area and the memory peripheral area.
3 more elements
4:
- The semiconductor device of claim 3, wherein the back end of the first intra-die via is extended to a back surface of the substrate while the front end of the first intra-die via is extended to a front surface of the dielectric layer, such that the first intra-die via is positioned penetrating along the substrate of the sensor die and the dielectric layer of the sensor die, and positioned on the landing pad.
5:
- The semiconductor device of claim 4, further comprising a transfer gate in the dielectric layer of the sensor die.
6:
- The semiconductor device of claim 5, further comprising a floating diffusion unit positioned in the substrate of the sensor die and positioned in a drain of the transfer gate.
7:
- The semiconductor device of claim 6, further comprising a color filter positioned on the substrate of the sensor die and above the sensor unit.
8:
- The semiconductor device of claim 7, further comprising a micro-lens positioned on the color filter.
9:
- The semiconductor device of claim 8, further comprising an upper layer positioned between the color filter and the substrate of the sensor die;
- wherein the upper layer comprises a bottom anti-reflective coating.
10:
- The semiconductor device of claim 9, further comprising an intervening insulating layer positioned between the memory die and the sensor die at a position that a front surface of the intervening insulating layer is in contact with the back surface of the memory die while a back surface of the intervening insulating layer is in contact with the front surface of the sensor die.
11:
- The semiconductor device of claim 10, wherein the landing pad is positioned in the intervening insulating layer, wherein a thickness of the landing pad is equal to a thickness of the intervening insulating layer.
12:
- The semiconductor device of claim 11, wherein the sensor unit includes a photodiode, wherein each of the first inter-die via and the first intra-die via has a tapered shape that a width thereof is gradually reduced from the back end to the front end.