Field effect transistor (fet) and method of manufacturing the same

A method of manufacturing a cell, the method comprising:

• forming a stack of alternating sacrificial semiconductor layers and semiconductor layers on a substrate;
• forming a hard mask on the stack;
• etching the stack through the hard mask to form trench in the stack, the trench dividing the stack into a first stack and a second stack, wherein the semiconductor layers in the first stack comprise a plurality of first prongs and the semiconductor layers in the second stack comprise a plurality of second prongs;
• epitaxially depositing silicon in the trench and along inner sidewalls of the first stack and the second stack, wherein the silicon comprises a first stem connected to the plurality of first prongs and a second stem connected to the plurality of second prongs;
• epitaxially depositing SiGe in the trench and along the first stem and the second stem;
• forming a dielectric wall in the trench;
• etching the sacrificial semiconductor layers in each of the first stack and the second stack;
• forming a first interfacial layer surrounding the first stem and the plurality of first prongs and a second interfacial layer surrounding the second stem and the plurality of second prongs;
• and
• forming a first metal gate on the first interfacial layer and surrounding the first stem and the plurality of first prongs and a second metal gate on the second interfacial layer and surrounding the second stem and the plurality of second prongs.

A method of manufacturing a cell, the method comprising:

• forming a stack of alternating sacrificial semiconductor layers and semiconductor layers on a substrate;
• forming a hard mask on the stack;
• etching the stack through the hard mask to form trench in the stack, the trench dividing the stack into a first stack and a second stack, wherein the semiconductor layers in the first stack comprise a plurality of first prongs and the semiconductor layers in the second stack comprise a plurality of second prongs;
• epitaxially depositing silicon to fill the trench;
• forming spacers on opposite sides of the trench;
• etching a portion of the silicon in the trench to form a first stem connected to the plurality of first prongs and a second stem connected to the plurality of second prongs;
• forming a dielectric wall in the portion of the silicon;
• etching the sacrificial semiconductor layers in each of the first stack and the second stack;
• forming a first interfacial layer surrounding the first stem and the plurality of first prongs and a second interfacial layer surrounding the second stem and the plurality of second prongs;
• and
• forming a first metal gate on the first interfacial layer and surrounding the first stem and the plurality of first prongs and a second metal gate on the second interfacial layer and surrounding the second stem and the plurality of second prongs.