Triac gate design for commutation sensitivity trade off improvement

A TRIAC, comprising:

• a first main terminal contact, a second main terminal contact, and a gate terminal contact;
• a first thyristor comprising a PNP transistor and a NPN transistor, with a base of the NPN transistor being connected to a collector of the PNP transistor and a base of the PNP transistor is connected to a collector of the NPN transistor, with an emitter-base junction of the NPN transistor having a forward-biased behavior modeled by a diode and a pinch-off resistance in parallel;
• a second thyristor comprising a PNP transistor and a NPN transistor, with the base of the NPN transistor being connected to the collector of the PNP transistor and the base of the PNP transistor being connected to the collector of the NPN transistor, with a shared semiconductor region forming the collector of the NPN transistor and the base of the PNP transistor;
• wherein a shared semiconductor region forms the collector of the NPN transistor and the base of the PNP transistor;
• wherein the gate terminal contact is connected to the base of the NPN transistor which is involved in the first thyristor, allowing control of current flow between the first and second main terminal contacts by modulating operation of the NPN and PNP transistors;
• and
• a serial resistance between the gate terminal contact and the first main terminal contact, thereby improving sensitivity and commutation of the TRIAC in certain operating conditions without causing significant degradation of sensitivity in other operating conditions.

A TRIAC, comprising:

• a first layer doped with a first conductivity type;
• a first region doped with a second conductivity type at a surface of the first layer;
• the first region forming a cathode of a first thyristor of the TRIAC and the first layer forming a gate of the first thyristor;
• a cathode metal layer in contact with the first region;
• a second region doped with the second conductivity type at the surface of the first layer;
• a gate metal layer in contact with the second region and in contact with the surface of the first layer;
• and
• a third region doped with the second conductivity type and extending from the second region in a position between the first region and where the gate metal layer contacts the surface of the first layer.

A TRIAC, comprising:

• a semiconductor substrate;
• a second P-type region formed in the semiconductor substrate;
• a third N-type region formed in the semiconductor substrate, adjacent to the second P-type region;
• a second N-type region formed in the semiconductor substrate on the second P-type region;
• a first P-type region formed in the semiconductor substrate on the second N-type region;
• a first N-type region formed in the semiconductor substrate, adjacent to the first P-type region;
• a fourth N-type region formed in the semiconductor substrate, adjacent to the first P-type region at a same level as the first N-type region and spaced apart therefrom;
• and
• a fifth N-type region formed in the semiconductor substrate, adjacent to the first P-type region at a same level as the first and fourth N-type regions and positioned therebetween but spaced apart therefrom;
• a first main terminal contact having a first portion disposed on the first N-type region and a second portion disposed on the first P-type region;
• a second main terminal contact disposed on the second P-type region and the third N-type region;
• and
• a gate terminal contact disposed partially on the first P-type region and partially on the fourth N-type region.

A method of making an improved TRIAC device, the method comprising:

• forming a TRIAC device by:
• doping a first layer with a first conductivity type, with the doping of the first layer having a greater concentration toward an upper portion thereof than toward a lower portion thereof;
• doping a first region with a second conductivity type at a surface of the first layer so that the first region forms a cathode of a first thyristor of the TRIAC device and the first layer forms a gate of the first thyristor;
• forming cathode metal layer in contact with the first region;
• doping a second region with the second conductivity type at the surface of the first layer;
• and
• forming a gate metal layer in contact with the second region and in contact with the surface of the first layer;
• and
• improving sensitivity and commutation of the TRIAC device in certain operating conditions without causing significant degradation of sensitivity in other operating conditions by increasing resistance along a current path between the gate metal layer and the cathode metal layer by forcing the current to traverse through the lower portion of the first layer.