Gate contact structure for a trench power mosfet with a split gate configuration

A method, comprising:

• forming a trench in a semiconductor substrate;
• lining sidewalls and a bottom of the trench with a first insulating layer;
• filling the trench with a first polysilicon material;
• selectively recessing the first polysilicon material in the trench at a first region of the semiconductor substrate to a first level;
• selectively recessing the first polysilicon material in the trench at a second region of the semiconductor substrate to a second level, said second level being greater in depth than said first level;
• selectively recessing an upper portion of the first insulating layer in said trench to a first depth in the first region and to a second depth in the second region in order to expose an upper portion of the recessed first polysilicon material in an upper portion of said trench;
• converting the exposed upper portion of the first polysilicon material in said trench to a polyoxide material;
• lining sidewalls and a bottom of the upper portion of said trench with a second insulating layer;
• and
• filling the upper portion of said trench with a second polysilicon material.

An integrated circuit transistor device, comprising:

• a semiconductor substrate providing a drain;
• a first doped region in the semiconductor substrate providing a source;
• a second doped region buried in the semiconductor substrate below the first doped region and providing a body;
• a trench extending into the semiconductor substrate and passing through the first and second doped regions;
• a polyoxide region within the trench;
• and
• a polygate region within the trench, said polygate region comprising:
• a first gate lobe on a first side of the polyoxide region, a second gate lobe on a second side of the polyoxide region opposite said first side, and a gate bridge extending over the polyoxide region;
• wherein, at a first region of the semiconductor substrate, the polyoxide region is recessed within the trench to a first level and the first and second gate lobes extend to a first depth within the trench;
• wherein, at a second region of the semiconductor substrate, the polyoxide region is recessed within the trench to a second level and the first and second gate lobes extend to a second depth within the trench;
• and
• wherein said second level is greater in depth than said first level the first and said second depth is greater than said first depth.

An integrated circuit transistor device, comprising:

• a semiconductor substrate providing a drain;
• a first doped region in the semiconductor substrate providing a source;
• a second doped region buried in the semiconductor substrate below the first doped region and providing a body;
• a trench extending into the semiconductor substrate and passing through the first and second doped regions;
• a polyoxide region within the trench;
• a polygate region within the trench, said polygate region comprising:
• a first gate lobe on a first side of the polyoxide region, a second gate lobe on a second side of the polyoxide region opposite said first side, and a gate bridge extending over the polyoxide region;
• wherein, at a first region of the semiconductor substrate, the gate bridge has a first thickness;
• wherein, at a second region of the semiconductor substrate, the gate bridge has a second thickness that is greater than the first thickness;
• a stack of insulating layers covering the transistor gate electrode, the trench and the semiconductor substrate;
• an opening at said second region of the semiconductor substrate aligned with the trench and extending through the stack of insulating layer and partially extending into the second thickness of the gate bridge;
• and
• a gate contact in said opening.