Crystallization temperature reduction of high-k dielectric layer
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShen-Yang LEE, Hsiang-Pi CHANG, Huang-Lin CHAO, Pinyen LIN
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Abstract
The present disclosure describes forming a crystalline high-k dielectric layer at a reduced crystallization temperature in a semiconductor device. The method includes forming a channel structure on a substrate, forming an interfacial layer on the channel structure, forming a first high-k dielectric layer on the interfacial layer, forming dipoles in the first high-k dielectric layer with a dopant, and forming a second high-k dielectric layer on the first high-k dielectric layer. The dopant includes a first metal element. The second high-k dielectric layer includes a second metal element different from the first metal element.
Claims20
A method, comprising:
- forming a channel structure on a substrate;
- forming an interfacial layer on the channel structure;
- forming a first high-k dielectric layer on the interfacial layer;
- forming dipoles in the first high-k dielectric layer with a dopant, wherein the dopant comprises a first metal element;
- and
- forming a second high-k dielectric layer on the first high-k dielectric layer, wherein the second high-k dielectric layer comprises a second metal element different from the first metal element.
A method, comprising:
- forming first and second channel structures on a substrate;
- forming an interfacial layer on the first and second channel structures;
- forming a first dielectric layer on the interfacial layer over the first and second channel structures;
- forming dipoles in the first dielectric layer over the first channel structure with a first dopant, wherein the first dopant comprises a first metal element;
- forming dipoles in the first dielectric layer over the second channel structure with a second dopant, wherein the second dopant comprises a second metal element different from the first metal element;
- and
- forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer comprises a third metal element different from the first and second metal elements.
A semiconductor device, comprising:
- a channel structure on a substrate;
- an interfacial layer on the channel structure;
- a first high-k dielectric layer on the interfacial layer over the channel structure, wherein the first high-k dielectric layer is doped with a first dopant comprising a first metal element and a second dopant comprising a second metal element different from the first metal element;
- and
- a second high-k dielectric layer on the first high-k dielectric layer, wherein the second high-k dielectric layer comprises the second metal element.
Dependencies are inferred from the claim text.