Lateral gate-all-around transistors, three-dimensional integrated circuit, and manufacturing method thereof

A CMOS (Complementary Metal-Oxide-Semiconductor) logic device, comprising three lateral gate-all-around transistor units superimposed in a vertical direction,

• wherein each lateral gate-all-around transistor unit comprises a gate connection of PMOS (Positive Metal-Oxide-Semiconductor) and NMOS (N-Metal-Oxide-Semiconductor) in CMOS, a gate oxide of NMOS, a gate oxide of PMOS, a wire, a source of NMOS, a source of PMOS, a drain of NMOS, a drain of PMOS, a channel of NMOS, and a channel of PMOS;
• the drain of NMOS is connected with the drain of PMOS through the wire, the source of NMOS and the source of PMOS are located on a same side;
• the drain of NMOS and the drain of PMOS are located on the same side;
• and
• the sources of the three lateral gate-all-around transistor units are located on the same side, and the drains of the three lateral gate-all-around transistor units are located on the same side.

A three-dimensional CMOS and non-logic gate, comprising two lateral gate-all-around transistor units superimposed in a vertical direction,

• wherein each lateral gate-all-around transistor unit comprises a gate connection of PMOS and NMOS in CMOS, a gate oxide of NMOS, a gate oxide of PMOS, a source of NMOS, a source of PMOS, a drain of NMOS, a drain of PMOS, a channel of NMOS, and a channel of PMOS;
• the source of NMOS and the drain of PMOS are located on the same side;
• the source of PMOS and the drain of NMOS are located on the same side;
• the source of PMOS and the drain of NMOS of one of the lateral gate-all-around transistor units are connected through a signal transmission terminal;
• the drain of PMOS of one of the lateral gate-all-around transistor units and the drain of PMOS of another lateral gate-all-around transistor units are connected through a first wire;
• the drain of NMOS of one of the lateral gate-all-around transistor units and the drain of NMOS of another lateral gate-all-around transistor units are connected through a first wire;
• and
• the source of PMOS of one of the lateral gate-all-around transistor units and the source of PMOS of another lateral gate-all-around transistor units are connected through a first wire.