VIAS and Via Rails for Source/Drain Metal Full Contact
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei-Hao Wu, Kuan Chen
Life of this patent
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei-Hao Wu, Kuan Chen
Estimating the term…
One aspect of the present disclosure pertains to a method of forming a semiconductor device. The method includes receiving a workpiece having a first metal gate stack over a first channel region, a second metal gate stack over a second channel region, a source/drain (S/D) feature between the first and second channel regions, and an S/D contact over the S/D feature. First and second dielectric caps are formed over the first and second metal gate stacks and a contact etch stop layer (CESL) is formed over the S/D contact and over the first and second dielectric caps. An interlayer dielectric (ILD) layer is formed over the CESL and an S/D via trench is formed through the ILD layer and the CESL. An S/D via is formed in the S/D via trench, making full surface contact with the S/D contact and partial surface contact with the first and second dielectric caps.
A method of forming a semiconductor device, comprising:
A method of forming a semiconductor device, comprising:
A semiconductor device, comprising:
Dependencies are inferred from the claim text.