Semiconductor device

A semiconductor device, comprising:

• an active pattern on a substrate;
• a plurality of source/drain patterns on the active pattern;
• a channel pattern electrically connecting the source/drain patterns and including stacked semiconductor patterns spaced apart from each other in a first direction perpendicular to an upper surface of the substrate;
• a gate pattern crossing between the source/drain patterns in a second direction parallel to the upper surface of the substrate, on the channel pattern, and having a main gate portion and sub-gate portions;
• and
• inner gate spacers between the sub-gate portions and the source/drain patterns,
• wherein a surface where each of the inner gate spacers is in contact with a corresponding one of the source/drain patterns has a concave or flat shape toward the source/drain patterns, and
• a first distance between adjacent source/drain patterns along a given one of the sub-gate portions in the second direction is greater than a second distance between the adjacent source/drain patterns along a given one of the semiconductor patterns in the second direction.

A semiconductor device, comprising:

• an active pattern on a substrate;
• a plurality of source/drain patterns on the active pattern;
• a channel pattern contacting the source/drain patterns and including stacked semiconductor patterns spaced apart from each other in a first direction perpendicular to an upper surface of the substrate;
• a gate pattern crossing between the source/drain patterns in a second direction parallel to the upper surface of the substrate, on the channel pattern, and having a main gate portion and sub-gate portions;
• and
• inner gate spacers having a first portion between the sub-gate portions and the source/drain patterns, and a second portion between the sub-gate portions and the channel pattern,
• wherein respective surfaces where the inner gate spacers are in contact with the source/drain patterns has a concave or flat shape toward the source/drain patterns,
• respective surfaces where the semiconductor patterns are in contact with the source/drain patterns has a concave cross-sectional shape toward the source/drain patterns, and
• a first distance between adjacent source/drain patterns along a given one of the sub-gate portions in the second direction is greater than a second distance between the adjacent source/drain patterns along a given one of the semiconductor patterns in the second direction.