Stacked two-transistor dynamic random access memory cell

An integrated circuit, comprising:

• one or more semiconductor structures, wherein at least one of the semiconductor structures comprises:
• a nanosheet field-effect transistor comprising a nanosheet stack structure;
• and
• a fin field-effect transistor comprising a set of vertical fins, wherein each of the vertical fins comprises an oxide semiconductor material;
• wherein the nanosheet field-effect transistor and the fin field-effect transistor are in a stacked configuration.

A semiconductor structure, comprising:

• a nanosheet field-effect transistor comprising a nanosheet stack structure and a first gate structure;
• and
• a fin field-effect transistor comprising:
• a set of vertical fins, wherein each of the vertical fins comprises an oxide semiconductor material;
• a second gate structure disposed on at least one vertical fin;
• a write word line disposed on the second gate structure;
• a write bit line disposed on the at least one vertical fin;
• and
• a metal contact connected to the first gate structure;
• wherein the nanosheet field-effect transistor and the fin field-effect transistor are in a stacked configuration.